Abstract: The present application discloses a shift, register circuit having a plurality of shift register units cascaded in series. The shift register circuit includes a first shift register unit and a second shift register unit. The first shift register unit includes a first pull-up node and a first output terminal and the second shift register unit includes a second pull-up node and a second output terminal. The shift register circuit includes a stabilizer circuit coupled to both the first shift register unit and the second shift register unit such that the first pull-up node is directly connected to the second pull-up node as a common pull-up node and configured to maintain a potential level of the common pull-up node stable during a stabilizing period when none of the first output terminal and the second output terminal output a turn-on signal.

Abstract: Disclosed is a method for manufacturing an ESD protection device. The ESD protection device includes a rectifier diode and an open-base bipolar transistor, the anode of the rectifier diode is the first doped region and the cathode of the rectifier diode is the semiconductor substrate, the emitter region, base region and collector region of the open-base bipolar transistor are the second doped region, the epitaxial semiconductor layer and semiconductor substrate, respectively, the first doped region and the second doped region extend through the doped region into the epitaxial semiconductor layer by a predetermined depth. The doped region can suppress the induced doped region around the second doped region, so that the parasitic capacitance of the open-base bipolar transistor is reduced and the response speed is improved.

Abstract: A display screen, a pair of glasses, a display system and a playing method are provided. The display screen includes a display control module and a display panel. The display control module controls the display panel to display multiple frames of images according to multiple predetermined playing codes. Each playing code corresponds to one frame of image. Each frame of image is displayed as normal image or interference image based on different logic values of the corresponding playing code. The multiple frames of images are divided into multiple consecutive frame groups.

Abstract: Embodiments of the present application provide a method and a device for acquiring ECG data, and an ECG detection system. A method for acquiring ECG data, comprising: acquiring ECG signals of heart; performing a first-stage amplification on the ECG signals, a multiple of the first-stage amplification including 5 to 10 times; performing band-pass filtering process within a first frequency range on the ECG signals on which the first-stage amplification has been performed, the first frequency range being 0.1 Hz to 50 Hz; performing a second-stage amplification on the ECG signals on which the band-pass filtering process has been performed, a multiple of the second-stage amplification including 40 to 50 times; performing analog-to-digital conversion on the ECG signals on which the second-stage amplification has been performed, to generate ECG digital signals; and outputting the ECG digital signals.

Abstract: An array substrate includes a base substrate, a thin film transistor and at least one photosensitive structure formed on the base substrate, the at least one photosensitive structure electrically connected to a drain electrode of the thin film transistor and configured to sense light intensity outside, and a common electrode formed on the base substrate on which the thin film transistor and the at least one photosensitive structure are formed. A method for manufacturing the array substrate, a control assembly and a display device are further disclosed.

Abstract: Disclosed are a semiconductor structure of an ESD protection device with low capacitance and a method for manufacturing the same. The method for manufacturing a semiconductor structure of an ESD protection device, comprising: forming a buried layer with a first doping type and a buried layer with a second doping type in a first region and a second region at a top surface of a semiconductor substrate with a first doping type, respectively; forming an epitaxial layer with a second doping type on the buried layer with the first doping type and the buried layer with the second doping type, wherein the buried layer with the first doping type and the buried layer with the second doping type are buried between the semiconductor substrate and the epitaxial layer, a first doped region with a first doping type is formed at a top of a third region on the buried layer with the second doping type located on the epitaxial layer.

Abstract: The present application discloses a display panel, comprising: a pixel structure constituted by a plurality of sub-pixels, wherein sub-pixels in each row are arranged in alignment, sub-pixels in every two adjacent rows are spaced in a column direction by a distance of X sub-pixels, 0<X<1, and a color of each sub-pixel differs from a color of an adjacent sub-pixel; a plurality of data lines arranged at column gaps between the sub-pixels; a plurality of touch signal lines arranged at gaps between the sub-pixels, wherein the plurality of touch signal lines are arranged in a different layer from the plurality of data lines and are insulated from the plurality of data lines; and a plurality of touch detection electrodes connected with the plurality of touch signal lines. The present application further discloses a method for manufacturing the above display panel and a display device.

Abstract: The present disclosure relates to a thin-film transistor, an array substrate, a display panel and a display device and fabrication methods thereof. The thin-film transistor includes a gate insulation layer, an active layer having a source region, a drain region, and a channel region, a first doping layer on the source region, a second doping layer on the drain region, and at least one third doping layer arranged between the first doping layer and the second doping layer, wherein the first, the second, and the third doping layers have same conductivity type, and wherein the third doping layer is positioned in the channel region and contacts the gate insulation layer, and the third doping layer does not contact the first doping layer and the second doping layer simultaneously, or the third doping layer is positioned on the channel region and only contacts the first or the second doping layer.

Abstract: Disclosed is a display panel, a method of manufacturing the same, and a display device. The display panel includes: a plurality of sub pixels arranged in rows and columns, wherein sub pixels in one of two adjacent rows of sub pixels are offset from sub pixels in the other row, respectively, in a column direction, and each sub pixel has a different color from an adjacent sub pixel; a plurality of data lines extending in the column direction in a column gap between the sub pixels; a plurality of touch signal lines provided in a gap between the sub pixels; and a plurality of touch detection electrodes electrically connected to the plurality of touch signal lines, respectively. The touch detection electrodes are used as a common electrode of the sub pixels, and the touch signal line is provided in a film layer between the common electrode and a pixel electrode of the sub pixel, respectively.

Abstract: The present disclosure describes a display Q_panel, a display panel and a manufacturing method thereof, as well as a display apparatus. The display Q_panel comprises a first and a second substrate for cell assembling to pre-form a plurality of display panels. The display Q_panel is provided, between the first substrate and the second substrate, with a blocking wall at the edge region on at least one side thereof, the blocking wall being located externally to the outmost cutting line on that side where it is located, and the sealant on that side being provided internally to the blocking wall. By providing a blocking wall externally to the outmost cutting line on the display Q_panel, the blocking wall blocks the spill-out of the sealant on that side, reduces the undesirable phenomena of sealant puncture, sealant break, etc. arising from the display panels after the cutting, can respond better to the Peel-off, Bending or other tests, and improves the robustness of glass cell assembling.

Abstract: An air filtration equipment, the air filtration equipment is installed in an ventilation area at an interface between indoor and outdoor spaces of a fixed space, the equipment including: a sensor configured to sense information on inhalable particles in outside air; at least one filtering layer configured to filter out inhalable particles in air entering from the ventilation area into the indoor space; and a control device connected with the sensor and the at least one filtering layer and configured to control the at least one filtering layer to expand according to the information sensed by the sensor, such that the expanded at least one filtering layer covers the ventilation area. Also, a screen window and a window are provided.

Abstract: The invention disclosed a method for manufacturing an electrode of a semiconductor device, comprising: forming a first interlayer dielectric layer having a first opening on a first surface of a semiconductor substrate; forming a first resist mask having a second opening on a surface of the first interlayer dielectric layer, wherein the first opening and the second opening are connected to form a first stacked opening; forming a first conductive layer on the first resist mask, wherein the first conductive layer comprises a first portion being located on a surface of the first resist mask and a second portion being located inside the first stacked opening; and removing the first resist mask, wherein the first portion of the first conductive layer is removed together with the first resist mask, and the second portion of the first conductive layer is retained as a first surface electrode.

Abstract: Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial semiconductor layer located on the semiconductor substrate and comprising a first doped region and a second doped region, wherein the semiconductor substrate and the first doped region are of a first doping type, the semiconductor buried layer, the epitaxial semiconductor layer and the second doped region are of a second doping type, the first doping type and the second doping type are opposite to each other, and the first doped region forms a plurality of interfaces with the epitaxial semiconductor layer. The disclosure improves protection performance and maximum current bearing capacity without increasing parasitic capacitance of the ESD protection device.

Abstract: Disclosed a transient voltage suppressor and a method for manufacturing the same. According to the transient voltage suppressor, an additional gate stack layer is introduced based on the prior transient voltage suppressor, and the diffusion isolation regions are reused as the conductive vias, so that, the gate stack layer, the first doped region, the conductive vias, and the second semiconductor layer constitute a MOS transistor being coupled in parallel to the Zener diode or the avalanche diode of the transient voltage suppressor. When the current of the I/O terminal is relatively large, the MOS transistor is turned on to share part of the current of the I/O terminal through the Zener diode or the avalanche diode, thereby protecting the Zener diode or the avalanche diode from being damaged due to excessive current. Thus, the robustness of the transient voltage suppressor is improved without increasing the manufacture cost.

Abstract: Disclosed is a method for manufacturing an ESD protection device. The method comprises: forming a first buried layer on the semiconductor substrate; forming a first epitaxial layer on the semiconductor substrate; forming a first doped region in the first epitaxial layer and forming a second doped region surrounding the first doped region in the first epitaxial layer, wherein the semiconductor substrate and the first doped region are both of a first doping type, the buried layer and the first epitaxial layer are both of a second doping type, the first doping type is opposite to the second doping type, the first doped region and the second doped region are formed using a same first mask. The method uses the same mask to form an emitter region of the open-base bipolar transistor, and to form a barrier doped region at the periphery of the emitter region, so that the manufacture cost is reduced and the parasitic capacitance of the ESD protection device is decreased.

Abstract: Embodiments of the present disclosure disclose an array substrate, a liquid crystal display panel and a display device. A strip shaped transparent and electrically conductive shielding electrode is arranged above a gate line, and an outer contour of a projection of the shielding electrode on a base substrate surrounds a projection of the gate line on the base substrate, and the shielding electrode is insulated from both a pixel electrode and the gate line. The shielding electrode can shield the electrical field above the gate line.

Abstract: A transient voltage suppressor can include: a semiconductor substrate; a first buried layer of a first type formed in and on the semiconductor substrate; a second buried layer of a second type formed in a first region of the first buried layer; a first epitaxial region of the second type formed on the second buried layer and a second epitaxial region of the first type formed on a second region of the first buried layer; a first doped region of the first type formed in the first epitaxial region and a second doped region of the second type formed in the second epitaxial region; a conductive channel extending from a surface of the second epitaxial region into the first buried layer; and a first electrode connected to the conductive channel, a second electrode connected to the first doped region, and a third electrode connected to the second doped region.

Abstract: A display panel and a manufacturing method thereof and a display device are provided. The display panel includes an array substrate and an opposed substrate that are opposite to each other, and a liquid crystal layer located between the array substrate and the opposed substrate. The display panel includes a display area and a non-display area, a phase shift layer is disposed at the non-display area of the array substrate, and the phase shift layer is configured to shift a phase of light passing through the phase shift layer. The display panel is used to solve color cast problem when a TFT-LCD displays a pure color, which is caused by cross color when the display panel is viewed at a side angle.

Abstract: An in-cell touch panel and a display device are disclosed. The in-cell touch panel includes an array substrate provided with a plurality of sub-pixels, and a plurality of gate lines and a plurality of data lines that are disposed on the array substrate, intersected with each other and insulated from each other, a plurality of self capacitive electrodes which are disposed in a same layer and independent of each other, and a plurality of touch lines connecting the self capacitive electrodes to the touch detection chip; the plurality of gate lines and the plurality of data lines are intersected with each other to define the plurality of sub-pixels; each of the sub-pixels includes a pixel electrode and is configured with a long side and a short side; and the touch lines are disposed along the direction of short sides of the sub-pixels.

Abstract: Disclosed is a method for manufacturing an ESD protection device. The ESD protection device includes a rectifier diode and an open-base bipolar transistor, the anode of the rectifier diode is the first doped region and the cathode of the rectifier diode is the semiconductor substrate, the emitter region, base region and collector region of the open-base bipolar transistor are the second doped region, the epitaxial semiconductor layer and semiconductor substrate, respectively, the first doped region and the second doped region extend through the doped region into the epitaxial semiconductor layer by a predetermined depth. The doped region can suppress the induced doped region around the second doped region, so that the parasitic capacitance of the open-base bipolar transistor is reduced and the response speed is improved.