Abstract: Disclosed is a nano-layered dual hydroxide-biological factor combined system for promoting nerve regeneration to repair a spinal cord injury. The preparation method therefor comprises: 1) synthesizing a nano-layered dual hydroxide CL1; and 2) co-incubating 10 mg CL1 and 200-2000 ng of biological factors NT3, VEGF or bFGF in a low-speed shaker at 4° C. for 2 hours using an ion exchange method, centrifuging same and then obtaining the precipitate. Experiments on transection and resorption spinal cord injury models show that this combined system has a significant recovery effect on the behavior of model mice, can reconstruct the neural circuit of a damaged area over time and achieves an ideal repair effect with regard to a spinal cord injury.

Abstract: A display substrate has a display area and a peripheral area. The display substrate includes a base substrate; a first insulating layer on the base substrate and in at least the peripheral area; a plurality of light emitting elements on the base substrate and in the display area; and an encapsulating layer on a side of the plurality of light emitting elements distal to the base substrate to encapsulate the plurality of light emitting elements. The encapsulating layer includes a first inorganic encapsulating sublayer extending from the display area into the peripheral area. The display substrate has a groove extending into the first insulating layer in the peripheral area, forming a first perimeter substantially surrounding the display area. The first inorganic encapsulating sublayer extends into at least a portion of the groove.

Abstract: A display substrate, a display panel, and a display device are provided. The display substrate includes: a base substrate; a plurality of sub-pixels in the display pixel region, wherein each sub-pixel includes a pixel driving circuit; a plurality of first dummy sub-pixel structures on the base substrate and in the first dummy pixel region, wherein at least one first dummy sub-pixel structure includes a compensation capacitor; and a plurality of scan signal lines arranged on the base substrate and configured to transmit a scan signal to the pixel driving circuit. At least one scan signal line extends through the display pixel region and the first dummy pixel region, and the at least one scan signal line is electrically connected to the pixel driving circuit of each sub-pixel in a row of sub-pixels and is further electrically connected to the compensation capacitor of the at least one first dummy sub-pixel structure.

Abstract: A display substrate has a display area and a peripheral area. The display substrate includes a base substrate; a first insulating layer on the base substrate and in at least the peripheral area; a plurality of light emitting elements on the base substrate and in the display area; and an encapsulating layer on a side of the plurality of light emitting elements distal to the base substrate to encapsulate the plurality of light emitting elements. The encapsulating layer includes a first inorganic encapsulating sublayer extending from the display area into the peripheral area. The display substrate has a groove extending into the first insulating layer in the peripheral area, forming a first perimeter substantially surrounding the display area. The first inorganic encapsulating sublayer extends into at least a portion of the groove.

Abstract: The present invention discloses a bullet with a negative Poisson's ratio effect and a method of designing thereof. The bullet includes a cylindrical section of the bullet having a negative Poisson's ratio design, and a conical tail of the bullet and a tip of the bullet each with a matching design; the cylindrical section of the bullet is a tubular structure having periodically alternating transverse and vertical holes; the tubular structure includes a plurality of holes, with a center axis of one hole being axially perpendicular to a center axis of another adjacent hole, that is, the axis of each hole being structurally orthogonal to an adjacent hole; and the holes in rows and columns are periodically arranged into the tubular structure, which is a tubular structure having the negative Poisson's ratio effect.

Abstract: The present disclosure provides a display panel and a method for manufacturing the same, and a display device. The display panel includes a display area and a non-display area surrounding the display area, wherein the non-display area includes: a substrate, at least a part of a surface of the substrate being non-planar; and an inorganic layer conformally located on one side of the substrate and in contact with the at least a part of the surface.

Abstract: Disclosed is a nano-layered dual hydroxide-biological factor combined system for promoting nerve regeneration to repair a spinal cord injury. The preparation method therefor comprises: 1) synthesizing a nano-layered dual hydroxide CL1; and 2) co-incubating 10 mg CL1 and 200-2000 ng of biological factors NT3, VEGF or bFGF in a low-speed shaker at 4° C. for 2 hours using an ion exchange method, centrifuging same and then obtaining the precipitate. Experiments on transection and resorption spinal cord injury models show that this combined system has a significant recovery effect on the behavior of model mice, can reconstruct the neural circuit of a damaged area over time and achieves an ideal repair effect with regard to a spinal cord injury.

Abstract: A metal mask, a display panel and a display device are proposed. The metal mask comprises an opening region and a peripheral region surrounding the opening region. The peripheral region is provided with a first groove, the first groove may surround the opening region. By arranging a first groove surrounding the opening region in the peripheral region, sagging of the metal mask during the fabrication of the display panel can be decreased effectively, and tension of the metal mask can be reduced, which improves the thickness uniformity of an inorganic encapsulation layer formed by using the metal mask, thereby achieving a higher production yield of the display panel.

Abstract: This disclosure relates to the field of display technologies and, in particular to a thin film packaging structure and a display panel. A thin film packaging structure includes a first inorganic packaging layer for covering a device to be packaged; an organic packaging layer formed at a side of the first inorganic packaging layer; a second inorganic packaging layer formed at a side of the organic packaging layer facing away from the first inorganic packaging layer; and at least one first inorganic adjusting layer formed at a side of the first inorganic packaging layer facing away from the device to be packaged. The at least one first inorganic adjusting layer has an elasticity modulus greater than that of the first inorganic packaging layer or the second inorganic packaging layer.

Abstract: A manufacturing method of a film layer, a display substrate and a manufacturing method thereof, and a device for manufacturing a display substrate are provided. The manufacturing method of a film layer includes: forming an organic layer on a substrate, in which the organic layer includes a flat portion and a slope portion around the flat portion; and heating the flat portion to cause a material of the flat portion to flow toward the slope portion, such that a thickness of a portion of the slope portion close to the flat portion is identical to a thickness of the flat portion to increase a size of the flat portion in a direction parallel to the substrate.

Abstract: A packaging method of a display panel, a display panel and an OLED display apparatus are provided. The packaging method includes: forming a dam on a first substrate provided with a component to be packaged, wherein the dam annularly surrounds the component to be packaged, and an intersection angle between an inner side surface of the dam and an upper surface of the first substrate is an acute angle; filling a region surrounded by the dam with a curable liquid; and aligning and assembling a second substrate with the first substrate on which the dam is formed.

Abstract: A packaging method of a display panel, a display panel and an OLED display apparatus are provided. The packaging method includes: forming a dam on a first substrate provided with a component to be packaged, wherein the dam annularly surrounds the component to be packaged, and an intersection angle between an inner side surface of the dam and an upper surface of the first substrate is an acute angle; filling a region surrounded by the dam with a curable liquid; and aligning and assembling a second substrate with the first substrate on which the dam is formed.

Abstract: A method and device for checking validity of memory access are provided. A cache is established and initialization is performed; a total cache position index is calculated; when a program performs memory access, a graded cache unit is addressed according to the total cache position index, and it is determined whether address information of the memory block is able to be read from the graded cache unit; when the address information is able to be read, it is determined whether an instrumentation-based memory checking tool is needed for checking the validity of the current memory access; when the address information is not able to be read, the validity of the current memory access is checked by an instrumentation-based memory checking tool, and the address information of the memory block is filled into the graded cache unit when the current memory access is determined to be valid.

Abstract: A method and device for checking validity of memory access are provided. A cache is established and initialization is performed; a total cache position index is calculated; when a program performs memory access, a graded cache unit is addressed according to the total cache position index, and it is determined whether address information of the memory block is able to be read from the graded cache unit; when the address information is able to be read, it is determined whether an instrumentation-based memory checking tool is needed for checking the validity of the current memory access; when the address information is not able to be read, the validity of the current memory access is checked by an instrumentation-based memory checking tool, and the address information of the memory block is filled into the graded cache unit when the current memory access is determined to be valid.