Patents by Inventor Shin-Cheng Lin

Shin-Cheng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200321249
    Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
    Type: Application
    Filed: June 22, 2020
    Publication date: October 8, 2020
    Inventors: Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 10790365
    Abstract: An LDMOS includes a body region disposed in the substrate and having a first conductivity type; a drift region disposed in the substrate and having a second conductivity type; a source region disposed in the body region and having the second conductivity type; a drain region disposed in the drift region and having the second conductivity type; an isolation region disposed in the drift region between the source region and the drain region; a gate disposed on the body region and the drift region; a source field plate electrically connected to the source region; a drain field plate electrically connected to the drain region; and a first gate plate electrically connected to the gate. The first gate plate is correspondingly disposed above the gate. The shapes of the first gate plate and the gate are substantially the same when viewed from a top view.
    Type: Grant
    Filed: February 23, 2018
    Date of Patent: September 29, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Hsin Lin, Yu-Hao Ho, Shin-Cheng Lin, Cheng-Tsung Wu
  • Publication number: 20200286744
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements. The fabrication methods for forming a package structure are provided.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 10, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Patent number: 10764475
    Abstract: A driving mechanism is provided, including a housing, a hollow frame, a holder, and a driving assembly. The frame is fixed to the housing and has a stop surface. The holder is movably disposed in the housing for holding the optical element. The driving assembly is disposed in the housing to drive the holder and the optical element moving along the optical axis of the optical element relative to the frame. Specifically, the stop surface is parallel to the optical axis to contact the holder and restrict the holder in a limit position.
    Type: Grant
    Filed: May 16, 2018
    Date of Patent: September 1, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Bing-Ru Song, Yi-Ho Chen, Chia-Pin Hsu, Chih-Wei Weng, Shin-Hua Chen, Chien-Lun Huang, Chao-Chun Chang, Shou-Jen Liu, Kun-Shih Lin, Nai-Wen Hsu, Yu-Cheng Lin, Shang-Yu Hsu, Yu-Huai Liao, Yi-Hsin Nieh, Shih-Ting Huang, Kuo-Chun Kao, Fu-Yuan Wu
  • Patent number: 10741537
    Abstract: A method of manufacturing a semiconductor structure includes forming a redistribution layer (RDL); forming a conductive member over the RDL; performing a first electrical test through the conductive member; disposing a first die over the RDL; performing a second electrical test through the conductive member; and disposing a second die over the first die and the conductive member.
    Type: Grant
    Filed: October 5, 2017
    Date of Patent: August 11, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COOMPANY LTD.
    Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
  • Publication number: 20200249379
    Abstract: A lens including a filter, an aperture stop, and a lens set sequentially arranged along a first direction is provided. The filter includes a central region and a peripheral region. The central region has a first light transmission band for a wavelength range of a visible light and a second light transmission band for a wavelength range of an infrared light. The peripheral region surrounds the central region. The peripheral region has a third light transmission band for the wavelength range of the infrared light and is substantially opaque to the visible light, and an area of one portion of the central region surrounded by the peripheral region is tapered toward the first direction.
    Type: Application
    Filed: November 14, 2019
    Publication date: August 6, 2020
    Applicant: Rays Optics Inc.
    Inventors: Chen-Cheng Lee, Chen-Yi Tsai, Shin-Jen Wang, Kuo-Hsiang Hung, Chih-Ling Lin, Meng-Wei Lin, Yu-Chia Lu
  • Publication number: 20200219870
    Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.
    Type: Application
    Filed: March 20, 2020
    Publication date: July 9, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Fu-Hsin CHEN, Shin-Cheng LIN, Yung-Hao LIN, Hsin-Chih LIN
  • Patent number: 10707322
    Abstract: A semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a gate electrode disposed over the barrier layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extend through at least portions of the barrier layer. The semiconductor device also includes a lining layer conformally disposed on bottom portions of the pair of source/drain electrodes.
    Type: Grant
    Filed: October 22, 2018
    Date of Patent: July 7, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Chih-Yen Chen, Shin-Cheng Lin, Hsin-Chih Lin
  • Patent number: 10692786
    Abstract: A semiconductor structure includes a substrate, a first insulating layer, a second insulating layer, a first seal ring structure, a second seal ring structure, and a passivation layer. The substrate has a chip region and a seal ring region. The first insulating layer is on the substrate. The second insulating layer is on the first insulating layer. The first seal ring structure is in the seal ring region and embedded in the first insulating layer and the second insulating layer, wherein the first seal ring structure includes a stack of metal layers. The second seal ring structure is in the seal ring region and embedded in the first insulating layer, wherein the second seal ring structure includes a polysilicon ring structure. The passivation layer is on the second insulating layer and the first seal ring structure.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: June 23, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Ting-You Lin, Chi-Li Tu, Shin-Cheng Lin, Yu-Hao Ho, Cheng-Tsung Wu
  • Patent number: 10692857
    Abstract: A semiconductor structure includes a substrate, a first III-V compound layer, a second III-V compound layer, a third III-V compound layer, and a fourth III-V compound layer. The top of the substrate includes a first region and a second region. The first III-V compound layer is in the first region. The second III-V compound layer is disposed over the first III-V compound layer. A first carrier channel is formed between the first III-V compound layer and the second III-V compound layer. The second III-V compound layer has a first thickness. The third III-V compound layer is in the second region. The fourth III-V compound layer is disposed over the third III-V compound layer. A second carrier channel is formed between the fourth III-V compound layer and the third III-V compound layer. The fourth III-V compound layer has a second thickness less than the first thickness.
    Type: Grant
    Filed: May 8, 2018
    Date of Patent: June 23, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Fu-Hsin Chen, Shin-Cheng Lin, Yung-Hao Lin, Hsin-Chih Lin
  • Patent number: 10692764
    Abstract: A device includes a substrate, and an alignment mark including a conductive through-substrate via (TSV) penetrating through the substrate.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 23, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsin Chang, Fang Wen Tsai, Jing-Cheng Lin, Wen-Chih Chiou, Shin-Puu Jeng
  • Patent number: 10665473
    Abstract: A package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Hsiang Lin, Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng, Arunima Banerjee
  • Patent number: 10644132
    Abstract: A semiconductor device is provided. The device may include a semiconductor layer; and a doped well disposed in the semiconductor layer and having a first conductivity type. The device may also include a drain region, a source region, and a body region, where the source and body regions may operate in different voltages. Further, the device may include a first doped region having a second conductivity type, the first doped region disposed between the source region and the doped well; and a second doped region having the first conductivity type and disposed under the source region. The device may include a third doped region having the second conductivity type and disposed in the doped well; and a fourth doped region disposed above the third doped region, the fourth doped region having the first conductivity type. Additionally, the device may include a gate and a field plate.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: May 5, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Shin-Cheng Lin
  • Publication number: 20200127116
    Abstract: A semiconductor device includes a channel layer disposed over a substrate, a barrier layer disposed over the channel layer, a gate electrode disposed over the barrier layer, and a pair of source/drain electrodes disposed on opposite sides of the gate electrode. The pair of source/drain electrodes extend through at least portions of the barrier layer. The semiconductor device also includes a lining layer conformally disposed on bottom portions of the pair of source/drain electrodes.
    Type: Application
    Filed: October 22, 2018
    Publication date: April 23, 2020
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Yen CHEN, Shin-Cheng LIN, Hsin-Chih LIN
  • Patent number: 10629475
    Abstract: A method for forming a semiconductor device is provided. A substrate is provided. An epitaxial layer is formed on the substrate. An insulation region and an active region are defined on the upper surface of the epitaxial layer. An insulation structure is formed within the insulation region by an ion implantation process and an etching process, wherein the insulation structure includes a first insulation structure and a second insulation structure. A gate is formed on the epitaxial layer and is disposed within the active region. A source and a drain are formed on opposite sides of the gate and within the active region. A semiconductor device is also provided.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: April 21, 2020
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Hsin-Chih Lin, Shin-Cheng Lin, Yung-Hao Lin
  • Publication number: 20200091029
    Abstract: A package structure and method for forming the same are provided. The package structure includes a semiconductor die formed over a first side of an interconnect structure, and the semiconductor die has a first height. The package structure also includes a first stacked die package structure formed over the first side of the interconnect structure, and the first stacked die package structure has a second height. The second height is greater than the first height. The package structure includes a lid structure formed over the semiconductor die and the first stacked die package structure. The lid includes a main portion and a protruding portion extending from the main portion, and the protruding portion is directly over the semiconductor die.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 19, 2020
    Inventors: Shin-Puu JENG, Po-Yao LIN, Feng-Cheng HSU, Shuo-Mao CHEN, Chin-Hua WANG
  • Publication number: 20200075569
    Abstract: A package structure and method for forming the same are provided. The package structure includes a first redistribution structure formed over a substrate, and the first redistribution structure includes a first conductive line, a second conductive line and a first overlapping conductive line between the first conductive line and the second conductive line. The first conductive line has a first width, the second conductive line which is parallel to the first conductive line has a second width, and the overlapping conductive line has a third width which is greater than the first width and the second width. The package structure includes a first package unit formed over the first redistribution structure, and the first package unit includes a first semiconductor die and a first die stack, and the first semiconductor die has a different function than the first die stack.
    Type: Application
    Filed: December 27, 2018
    Publication date: March 5, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Puu JENG, Po-Yao LIN, Shuo-Mao CHEN, Feng-Cheng HSU, Chia-Hsiang LIN
  • Patent number: 10573738
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: February 25, 2020
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Publication number: 20200058571
    Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate. The semiconductor package further includes a first chip and a second chip mounted on the package substrate. The thickness of the first chip is different from that of the second chip. In addition, the semiconductor package includes a heat spreader attached on top of the first chip and top of the second chip. A first portion of the heat spreader over the first chip and a second portion of the heat spreader over the second chip have the same thickness.
    Type: Application
    Filed: February 14, 2019
    Publication date: February 20, 2020
    Inventors: Chin-Hua WANG, Po-Yao LIN, Feng-Cheng HSU, Shin-Puu JENG, Wen-Yi LIN, Shu-Shen YEH
  • Patent number: D891504
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: July 28, 2020
    Assignee: TDK TAIWAN CORP.
    Inventors: Fu-Yuan Wu, Kun-Shih Lin, Shang-Yu Hsu, Yi-Ho Chen, Shih-Ting Huang, Shou-Jen Liu, Chien-Lun Huang, Yi-Hsin Nieh, Chen-Chi Kuo, Chia-Pin Hsu, Yu-Huai Liao, Shin-Hua Chen, Yu-Cheng Lin, Shao-Chung Chang, Kuo-Chun Kao, Chia-Hsiu Liu, Chao-Chun Chang, Yuan-Shih Liao