Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

Abstract: The invention relates to a versatile optical storage driving device for multimedia video system incorporated with functions of a compact-disc (CD) driver, a digital versatile disc (DVD) driver, a frequency modulated (FM) radio and a MP3 music CD player, such versatile optical storage driving device is characterized in the possibility of being a built-in and/or external-connected CD-ROM/CD-RW driver operated through the operating system with personal computer (PC) on or being a stand-alone CD-ROM/CD-RW driver operated by itself with PC off, and being a digital picture viewer and video player capable of displaying photograph/picture and video disc through a built-in/external-connected display device as well as being a digital recorder capable of recording video signal, such device comprises: a video/audio input/output selector; a video/audio encoder/decoder; a microprocessor; a optical storage device; a memory card reader; a display controller; a status display; a power amplifier; and a speaker.

Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

Abstract: A semiconductor device with multiple strap-contact configurations for a memory cell array. An array with memory cells interconnected with bit-lines, control-gate lines, erase gate lines, common-source lines, and word-lines is provided. In one aspect of an illustrative embodiment, a strap-contact corridor is spaced at n bit-line intervals (n>1) across the array. The strap-contact corridor comprises strap-contact cells, which provide electrical interconnection between control-gate lines, erase gate lines, common-source lines, and word-lines and their respective straps.

Abstract: A semiconductor device with multiple strap-contact configurations for a memory cell array. An array with memory cells interconnected with bit-lines, control-gate lines, erase gate lines, common-source lines, and word-lines is provided. In one aspect of an illustrative embodiment, a strap-contact corridor is spaced at n bit-line intervals (n>1) across the array. The strap-contact corridor comprises strap-contact cells, which provide electrical interconnection between control-gate lines, erase gate lines, common-source lines, and word-lines and their respective straps.

Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.

Abstract: A buffer is disclosed. The buffer may include a buffer controller for buffering a refresh signal enabled in an auto-refresh operation synchronously with an external clock signal, a logic circuit for performing a logic operation with respect to an output signal from the buffer controller and a specific signal to output a control signal, and an internal clock generator controlled by the control signal from the logic circuit for buffering the external clock signal and generating internal clock signals.

Abstract: A buffer is disclosed. The buffer may include a buffering circuit for buffering an input signal, a buffer control circuit for outputting a first control signal which enables the buffering circuit responsive to an enable signal, and a second control signal which is enabled after the lapse of a predetermined period from a point of enable timing of the first control signal, and a logic unit for performing a logic operation with respect to an output signal from the buffering circuit and the second control signal from the buffer control circuit.

Abstract: An input buffer circuit of a semiconductor memory device, wherein a corresponding memory chip is not always selected regardless of a chip select signal in a power-down operating mode or a self-refresh operating mode. Accordingly, the problem of semiconductor memory device malfunctions in the power-down operating mode or the self-refresh operating mode can be prevented.

Abstract: A memory device including a parallel test circuit can overcome a channel deficiency phenomenon of test equipment by reducing the number of input/output pads. The memory device including a parallel test circuit comprises a burst length regulating block, a parallel test block, an output block and a plurality of input/output pads. The burst length regulating block sets a second burst length at a test mode which is longer than a first burst length at a normal mode. The parallel test block compresses data and tests the compressed data by a repair unit. The output block sequentially outputs data outputted from at least two or more parallel test blocks depending on the second burst length. The plurality of input/output pads externally output data outputted from the output block.

Abstract: A solar cell array control device has a plurality of solar cell modules, a bidirectional DC converter, at least a voltage sensor and a control unit. The bidirectional DC converter corresponds to and is electrically connected to the solar cell modules to connect these solar cell modules in series to form a solar cell array. The voltage sensor is electrically connected to the solar cell modules, and can generate an abnormal voltage when detecting that one of the solar cell modules is abnormal. The control unit is electrically connected to the voltage sensor and the bidirectional DC converter, and outputs a pulse width modulation signal by detecting the abnormal voltage to control the bidirectional DC converter for compensating the conversion current and thus enhancing the output power of this solar cell module.

Abstract: The invention relates to a versatile optical storage driving device for multimedia video system incorporated with functions of a compact-disc (CD) driver, a digital versatile disc (DVD) driver, a frequency modulated (FM) radio and a MP3 music CD player, such versatile optical storage driving device is characterized in the possibility of being a built-in and/or external-connected CD-ROM/CD-RW driver operated through the operating system with personal computer (PC) on or being a stand-alone CD-ROM/CD-RW driver operated by itself with PC off, and being a digital picture viewer and video player capable of displaying photograph/picture and video disc through a built-in/external-connected display device as well as being a digital recorder capable of recording video signal, such device comprises: a video/audio input/output selector; a video/audio encoder/decoder; a microprocessor; a optical storage device; a memory card reader; a display controller; a status display; a power amplifier; and a speaker.

Abstract: The invention relates to a multi-functional optical disk driving device used in personal computer (PC), which has functions of a compact-disk (CD) driver, a digital versatile disk (DVD) driver, a frequency modulated (FM) radio, a MP3 music CD player, such device comprises: a multi-functional vision process controller (VPC) having a PC power on status detector; a microprocessor; a bus switch; an optical disk server; and a connecting device. The multi-functional optical disk driving device of present invention is characterized in that the device can perform these functions without making use the control from the operating system (OS) of a personal computer even if the PC is off and these functions are performed by the PC when the PC is on.

Abstract: A clock control circuit prevents glitches when turning a clock signal back on after being turned off following a period of system inactivity and includes a first flip-flop, a second flip-flop, and a NAND gate. The first flip-flop receives a direct input beginclk signal and a clock-triggered stopclk signal. The first flip-flop also has an output Q.sub.1. A change in the beginclk signal is indicative of the start of a clock signal. The periodic signal is for triggering the storage of the stopclk signal in the first flip-flop. The second flip-flop receives the direct input beginclk signal and the output Q.sub.1 of the first flip-flop as a clock-triggered input. The second flip-flop also has an output Q.sub.2. The periodic signal is also for triggering the storage of the output Q.sub.1 of the first storage element in the second storage element. The NAND gate receives the output Q.sub.2 of the second flip-flop as a first input. The output Q.sub.

Abstract: A circuit board surface treatment equipment, which includes an upper solution chamber and a bottom solution chamber defined within a machine base at different elevations, a set of conveying rollers and upper and lower bumper rollers arranged in the upper solution chamber and controlled to deliver circuit boards through the upper solution chamber for treatment, upper and lower pressure-balanced water knives respectively mounted in gaps in between the conveying rollers and controlled to eject a surface treatment solution onto the circuit boards, and water level control switch means which open the passage between the upper solution chamber and the bottom solution chamber for letting the surface treatment solution flow from the upper solution chamber to the bottom solution chamber when the level of surface treatment solution in the upper solution chamber surpasses a predetermined high level.

Abstract: A game ball for use in playing such games as baseball or softball comprises a spherical core made of PVC foam, a core cover of an ethylene copolymer, the core cover having a corrugated or rough surface, yarn windings and an outer leather cover, the ball having lower production cost and good durability in addition to essentially the same playing characteristics as conventional balls.