Patents by Inventor Shin Fujita

Shin Fujita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040169623
    Abstract: A data line driving circuit 200 has a shift resistor unit 210 in which respective shift resistor unit circuits Ua1 to Uan+2 are in cascade connection with each other, and an output signal control unit 220 comprising respective operational unit circuits Ub1 to Ubn+1. A NAND circuit 514 controls an enabling period of a negative sampling signal based on an output signal from a NAND circuit 511 in an subsequent-stage operational unit circuit.
    Type: Application
    Filed: July 30, 2003
    Publication date: September 2, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shin Fujita
  • Publication number: 20040169797
    Abstract: The invention enhances the aperture ratio of an electro-optical panel. A light-shielding layer includes a first light-shielding layer and second light-shielding layers. The first light-shielding layer is formed so as to overlap a plurality of scanning lines and a plurality of data lines. Each of the second light-shielding layers is provided on the downside of the direction of rubbing with respect to the corresponding projecting pattern. Each of the projecting patterns is formed such that part thereof overlaps the corresponding data line. The second light-shielding layers overlap the first light-shielding layer. All or part of each of the second light-shielding layers can also function as the first light-shielding layer to increase the area of an aperture.
    Type: Application
    Filed: February 18, 2004
    Publication date: September 2, 2004
    Applicant: SEIKO EPSON CORPORATON
    Inventors: Shin Fujita, Toru Nimura
  • Patent number: 6784880
    Abstract: The invention prevents shift register circuits from malfunctioning. A distribution circuit outputs a trailing trigger pulse DTP and a leading trigger pulse UTP. A trailing edge control circuit and a leading edge control circuit delay the trailing trigger pulse DTP and the leading trigger pulse UTP, respectively. The delay time of each of these control circuits can be set. These delay times are determined according to a threshold voltage of a TFT constituting a shift register. An inverted clock signal CLYINV is generated according to output signals of the control circuits. The shift register is driven by a clock signal CLY and an inverted clock signal CLYINV.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: August 31, 2004
    Assignee: Seiko Epson Corporation
    Inventors: Shin Fujita, Tokuro Ozawa
  • Publication number: 20040141136
    Abstract: An electro-optic device is provided that is capable of preventing an interference of reflected lights from a light reflecting film and avoiding the occurrence of glare and chrominance non-uniformity among pixels, and an electronic apparatus using the electro-optic device. In a TFT array substrate of a reflective or transflective electro-optic device, a lower-side recess/projection forming film 13a, is formed in each of pixels 100a in the form of a matrix pattern so that a recess/projection pattern to scatter light is formed on the surface of a light reflecting film. The pixels are grouped into a plurality of units, each including a plurality of pixels, and the recess/projection pattern is formed to provide a different pattern for each pixel at least in each of the units. Different recess/projection patterns are obtained, for example, by rotating the recess/projection pattern for a pixel as a reference.
    Type: Application
    Filed: September 29, 2003
    Publication date: July 22, 2004
    Applicant: Seiko Epson Corporation
    Inventors: Toru Nimura, Shin Fujita
  • Patent number: 6753839
    Abstract: The present invention provides an electro-optical panel that is capable of effectively exhibiting the features of the construction in which two transistor elements are used per pixel, and an electronic device using the electro-optical panel. A pixel includes a P-channel thin-film transitor (TFT) in which the gate electrode is connected to a scanning line, and an N-channel TFT in which the gate electrode is connected to a scanning line. When the P-channel TFT and the N-channel TFT are turned on, the voltage of an image signal supplied to a data line is written into a holding capacitor HC and a holding capacitor LC. The holding capacitor HC is connected to the drain electrode of the N-channel TFT. Also, the holding capacitor HC is connected to the drain electrode of the P-channel TFT via a wiring line L. Since the wiring line L is formed of a low-resistance material, the time constant when the image signal is written into the holding capacitor HC via the P-channel TFT can be decreased.
    Type: Grant
    Filed: December 14, 2001
    Date of Patent: June 22, 2004
    Assignee: Seiko Epson Corporation
    Inventor: Shin Fujita
  • Publication number: 20040107390
    Abstract: To facilitate the estimation of the delay time between an input and an output. Inverters INV1 and INV4 generate a reference signal R and a signal to-be-corrected H on the basis of an input positive-logic signal Pin and an input negative-logic signal Nin. Since the reference signal R is transferred through a wiring line Lp, it undergoes no delay in the process of the transfer. On the other hand, the signal to-be-corrected H undergoes the influence of the reference signal R and has its phase corrected by a NAND circuit 11 and a NOR circuit 12.
    Type: Application
    Filed: July 30, 2003
    Publication date: June 3, 2004
    Applicant: Seiko Epson Corporation
    Inventor: Shin Fujita
  • Publication number: 20040105140
    Abstract: The invention miniaturizes a liquid crystal panel and thus provides a lightweight panel. A TFT provided so as to correspond to intersections of data lines and scanning lines. A dummy pixel area does not contribute to image display, while an effective pixel area contributes to image display. An identification pattern represents a sequence of scanning lines. By forming the identification pattern in the dummy pixel area, the data lines and a scanning line driving circuit can be provided closer to each other, and a picture frame area can be reduced.
    Type: Application
    Filed: October 3, 2003
    Publication date: June 3, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shin Fujita
  • Publication number: 20040094764
    Abstract: The invention provides an active matrix type electro-optical device and an electronic apparatus using the same capable of preventing interference of light due to contact holes and interference of reflecting light from light-reflecting film. In a thin film transistor (TFT) array substrate of a reflective active matrix type electro-optical device, a light-reflecting film can be formed in a contact hole, but positions of the contact holes for electrically connecting a pixel electrode to a drain electrode, and irregular pattern for scattering light formed on the surface of the reflection film by a lower side irregularity-formation film are different in each of pixels formed in a matrix.
    Type: Application
    Filed: September 30, 2003
    Publication date: May 20, 2004
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Toru Nimura, Shin Fujita
  • Patent number: 6703856
    Abstract: The invention performs an accurate testing in order to determine the presence or absence of a defect in a wiring and electrodes in an electro-optical device. A test method is provided for testing an electro-optical device that includes a capacitor arranged at an intersection of each scanning line and each data line. A test switching element connected between the data line and a reading signal-line is turned on after storing a charge responsive to a data signal in the capacitor so that the voltage responsive to the charge stored in the capacitor is output to the reading signal-line. The timing of switching on the test switching element is set to be different from the timing of a level change of a test clock pulse that defines the operation of a test circuit.
    Type: Grant
    Filed: November 28, 2001
    Date of Patent: March 9, 2004
    Assignee: Seiko Epson Corporation, Ltd.
    Inventor: Shin Fujita
  • Publication number: 20040012552
    Abstract: To inspect for display defects before mounting a data-line driver IC. An image-signal supplying circuit 250A includes wiring for connecting data lines 3-1 to 3-n and connection terminals P1 to Pn of a data-line driver IC; image-signal lines LT1 to LTj; transfer gates for connecting or disconnecting the wiring and the image-signal lines based on a control signal KC; control lines LC1 and LC2; a pull-down resistor 251 connected to the control line LC1; and a pull-up resistor 252 connected to the control line LC2.
    Type: Application
    Filed: April 4, 2003
    Publication date: January 22, 2004
    Applicant: Seiko Epson Corporation
    Inventor: Shin Fujita
  • Publication number: 20030231734
    Abstract: To provide a shift register that reliably operates even when the driving ability of a clock signal is low. A data-line driving circuit 200 includes a shift-register section 210, which has serially-connected shift-register unit circuits Ua1 to Uan+2, and a clock-signal control section 220, which has serially-connected control unit circuits Uc1 to Ucn+2. Each control unit circuit Uc1 to Ucn+2 supplies an X clock-signal XCK and an inverted X clock-signal XCKB to the corresponding shift-register unit circuit Ua1 to Uan+2 in a period of time when either one of signal voltages at nodes A1, A2, . . . at the prior and subsequent stages is active.
    Type: Application
    Filed: April 4, 2003
    Publication date: December 18, 2003
    Applicant: Seiko Epson Corporation
    Inventors: Shin Fujita, Shinsuke Fujikawa
  • Publication number: 20030180975
    Abstract: The invention provides an electrooptic device and an electronic apparatus, in which the electrical characteristics of many thin-film switching elements formed in a substrate to support an electrooptic material can be accurately inspected. The invention also provides a method for making the electrooptic device. In a TFT array substrate of a liquid crystal device, an inspection TFT is formed in one of dummy pixels disposed at the periphery of a pixel region. A pixel electrode connected to a drain region of the TFT functions as a first inspection pad. In an adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a data line functions as a second inspection pad. In another adjacent dummy pixel, the pixel electrode electrically connected to an extended portion of a scan line via a junction electrode functions as a third inspection pad.
    Type: Application
    Filed: January 22, 2003
    Publication date: September 25, 2003
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shin Fujita
  • Publication number: 20020101398
    Abstract: The present invention provides an electro-optical panel that is capable of effectively exhibiting the features of the construction in which two transistor elements are used per pixel, and an electronic device using the electro-optical panel. A pixel includes a P-channel thin-film transitor (TFT) in which the gate electrode is connected to a scanning line, and an N-channel TFT in which the gate electrode is connected to a scanning line. When the P-channel TFT and the N-channel TFT are turned on, the voltage of an image signal supplied to a data line is written into a holding capacitor HC and a holding capacitor LC. The holding capacitor HC is connected to the drain electrode of the N-channel TFT. Also, the holding capacitor HC is connected to the drain electrode of the P-channel TFT via a wiring line L. Since the wiring line L is formed of a low-resistance material, the time constant when the image signal is written into the holding capacitor HC via the P-channel TFT can be decreased.
    Type: Application
    Filed: December 14, 2001
    Publication date: August 1, 2002
    Applicant: Seiko Epson Corporation
    Inventor: Shin Fujita
  • Publication number: 20020070750
    Abstract: The invention performs an accurate testing in order to determine the presence or absence of a defect in a wiring and electrodes in an electro-optical device. A test method is provided for testing an electro-optical device that includes a capacitor arranged at an intersection of each scanning line and each data line. A test switching element connected between the data line and a reading signal-line is turned on after storing a charge responsive to a data signal in the capacitor so that the voltage responsive to the charge stored in the capacitor is output to the reading signal-line. The timing of switching on the test switching element is set to be different from the timing of a level change of a test clock pulse that defines the operation of a test circuit.
    Type: Application
    Filed: November 28, 2001
    Publication date: June 13, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventor: Shin Fujita
  • Publication number: 20020015031
    Abstract: To maintain image quality when a field frequency is dynamically changed. In an image display area AA, control lines 4a are arranged respectively corresponding to scanning lines 3a, and TFTs 50 and 51, a pixel electrode 9a, and a storage capacitor 52 are arranged at each intersection of one of data lines 6a and scanning lines 3a. A control signal SC supplied through the control line 4a controls the TFT 51 for an on and off operation. A timing signal generator circuit 300 activates the control signal SC when a field frequency is not higher than 60 Hz, and deactivates the control signal SC when a field frequency is above 60 Hz. In this way, whether or not to connect the storage capacitor 52 to the pixel electrode 9a is determined.
    Type: Application
    Filed: July 24, 2001
    Publication date: February 7, 2002
    Applicant: SEIKO EPSON CORPORATION
    Inventors: Shin Fujita, Tokuro Ozawa
  • Publication number: 20010003418
    Abstract: The invention prevents shift register circuits from malfunctioning. A distribution circuit outputs a trailing trigger pulse DTP and a leading trigger pulse UTP. A trailing edge control circuit and a leading edge control circuit delay the trailing trigger pulse DTP and the leading trigger pulse UTP, respectively. The delay time of each of these control circuits can be set. These delay times are determined according to a threshold voltage of a TFT constituting a shift register. An inverted clock signal CLYINV is generated according to output signals of the control circuits. The shift register is driven by a clock signal CLY and an inverted clock signal CLYINV.
    Type: Application
    Filed: December 8, 2000
    Publication date: June 14, 2001
    Inventors: Shin Fujita, Tokuro Ozawa