Patents by Inventor Shin-Hua Chao
Shin-Hua Chao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10867899Abstract: A method of manufacturing a semiconductor package includes: (1) providing a first passivation layer on a carrier; (2) patterning the first passivation layer to define a first hole; (3) disposing a first seed layer on the first hole; (4) disposing a first conductive layer on the first seed layer; (5) replacing the carrier with a second passivation layer; (6) patterning the second passivation layer to define a second hole exposing the first seed layer; and (7) disposing a second conductive layer on the exposed first seed layer through the second hole.Type: GrantFiled: October 30, 2018Date of Patent: December 15, 2020Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Fu Sung, Shin-Hua Chao, Ming-Chi Liu, Hung-Sheng Chen
-
Publication number: 20190067181Abstract: A method of manufacturing a semiconductor package includes: (1) providing a first passivation layer on a carrier; (2) patterning the first passivation layer to define a first hole; (3) disposing a first seed layer on the first hole; (4) disposing a first conductive layer on the first seed layer; (5) replacing the carrier with a second passivation layer; (6) patterning the second passivation layer to define a second hole exposing the first seed layer; and (7) disposing a second conductive layer on the exposed first seed layer through the second hole.Type: ApplicationFiled: October 30, 2018Publication date: February 28, 2019Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Fu SUNG, Shin-Hua CHAO, Ming-Chi LIU, Hung-Sheng CHEN
-
Patent number: 10141252Abstract: A semiconductor package includes: a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining a through hole extending from the first surface to the second surface, the through hole being further defined by a first sidewall and a second sidewall of the passivation layer; a first conductive layer on the first surface of the passivation layer and the first sidewall; a second conductive layer on the second surface of the passivation layer and the second sidewall; and a third conductive layer between the first conductive layer and the second conductive layer.Type: GrantFiled: February 16, 2017Date of Patent: November 27, 2018Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Yuan-Fu Sung, Shin-Hua Chao, Ming-Chi Liu, Hung-Sheng Chen
-
Publication number: 20180233443Abstract: A semiconductor package includes: a passivation layer having a first surface and a second surface opposite to the first surface, the passivation layer defining a through hole extending from the first surface to the second surface, the through hole being further defined by a first sidewall and a second sidewall of the passivation layer; a first conductive layer on the first surface of the passivation layer and the first sidewall; a second conductive layer on the second surface of the passivation layer and the second sidewall; and a third conductive layer between the first conductive layer and the second conductive layer.Type: ApplicationFiled: February 16, 2017Publication date: August 16, 2018Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Yuan-Fu SUNG, Shin-Hua CHAO, Ming-Chi LIU, Hung-Sheng CHEN
-
Patent number: 8889488Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.Type: GrantFiled: September 3, 2013Date of Patent: November 18, 2014Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Shin-Hua Chao, Chao-Yuan Liu, Hui-Ying Hsieh, Chih-Ming Chung
-
Publication number: 20140011325Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.Type: ApplicationFiled: September 3, 2013Publication date: January 9, 2014Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Shin-Hua CHAO, Chao-Yuan LIU, Hui-Ying HSIEH, Chih-Ming CHUNG
-
Patent number: 8546950Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.Type: GrantFiled: November 16, 2010Date of Patent: October 1, 2013Assignee: Advanced Semiconductor Engineering Inc.Inventors: Shin-Hua Chao, Chao-Yuan Liu, Hui-Ying Hsieh, Chih-Ming Chung
-
Publication number: 20120032341Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a substrate, a semiconductor element, a package body and a conductive part. The substrate has an electrical contact. The semiconductor element is disposed on the substrate. The package body covers the semiconductor element and defines a through hole from which the electrical contact is exposed. Wherein, the package body includes a resin body and a plurality of fiber layers. The fiber layers are disposed in the resin body and define a plurality of fiber apertures which is arranged as an array. The conductive part is electrically connected to the substrate through the through hole.Type: ApplicationFiled: November 16, 2010Publication date: February 9, 2012Inventors: Shin-Hua CHAO, Chao-Yuan LIU, Hui-Ying HSIEH, Chih-Ming CHUNG
-
Patent number: 8059422Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.Type: GrantFiled: July 31, 2008Date of Patent: November 15, 2011Assignees: Advanced Semiconductor Engineering, Inc., ASE Electronics Inc.Inventors: Ho-Ming Tong, Shin-Hua Chao, Ming-Chiang Lee, Tai-Yuan Huang, Chao-Yuan Liu, Yung-Cheng Huang, Teck-Chong Lee, Jen-Chieh Kao, Jau-Shoung Chen
-
Publication number: 20100289133Abstract: The present invention relates to a stackable package having an embedded interposer and a method for making the same. The package includes a substrate, a chip, a first embedded interposer, a circuit layer and a solder mask. The substrate has an upper surface, a bottom surface and at least one connecting pad. The connecting pad is disposed adjacent to the upper surface. The chip is disposed adjacent to the upper surface of the substrate, and is electrically connected to the substrate. The first embedded interposer encapsulates the upper surface of the substrate and the chip. The to first embedded interposer includes at least one plating through hole. The plating through hole penetrates through the first embedded interposer, and is connected to the connecting pad of the substrate. The circuit layer is disposed adjacent to the first embedded interposer, and the plating through hole is connected to the circuit layer. The circuit layer includes at least one pad.Type: ApplicationFiled: March 19, 2010Publication date: November 18, 2010Inventors: Shin-Hua Chao, Teck-Chong Lee, Shing-Cheng Liang
-
Patent number: 7614888Abstract: A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.Type: GrantFiled: September 24, 2008Date of Patent: November 10, 2009Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Ho-Ming Tong, Shin-Hua Chao, Ming-Chiang Lee, Tai-Yuan Huang, Chao-Yuan Liu, Yung-Cheng Huang, Teck-Chong Lee, Jen-Chieh Kao, Jau-Shoung Chen
-
Publication number: 20090087947Abstract: A flip chip package process is provided. First, a substrate strip including at least one substrate is provided. Next, at least one chip is disposed on the substrate, and the chip is electrically connected to the substrate. Then, a stencil having at least one opening and an air slot hole is disposed on an upper surface of the substrate strip, an air gap is formed between the stencil and the substrate strip, the air gap connects the opening and the air slot hole, and the chip is located in the opening. Finally, a liquid compound is formed into the opening of the stencil to encapsulate the chip, and a vacuum process is performed through the air slot hole and the air gap, so as to prevent the air inside the opening from being encapsulated by the liquid compound to become voids.Type: ApplicationFiled: September 24, 2008Publication date: April 2, 2009Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Ho-Ming Tong, Shin-Hua Chao, Ming-Chiang Lee, Tai-Yuan Huang, Chao-Yuan Liu, Yung-Cheng Huang, Teck-Chong Lee, Jen-Chieh Kao, Jau-Shoung Chen
-
Publication number: 20090075027Abstract: A manufacturing process for a thermally enhanced package is disclosed. First, a substrate strip including at least a substrate is provided. Next, at least a chip is disposed on an upper surface of the substrate, and the chip is electrically connected to the substrate. Then, a prepreg and a heat dissipating metal layer are provided, and the heat dissipating metal layer is disposed on a first surface of the prepreg and a second surface of the prepreg faces toward the chip. Finally, the prepreg covers the chip by laminating the prepreg and the substrate.Type: ApplicationFiled: July 31, 2008Publication date: March 19, 2009Applicants: ADVANCED SEMICONDUCTOR ENGINEERING, INC., ASE ELECTRONICS INC.Inventors: Ho-Ming Tong, Shin-Hua Chao, Ming-Chiang Lee, Tai-Yuan Huang, Chao-Yuan Liu, Yung-Cheng Huang, Teck-Chong Lee, Jen-Chieh Kao, Jau-Shoung Chen
-
Patent number: 7445944Abstract: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.Type: GrantFiled: December 28, 2006Date of Patent: November 4, 2008Assignee: ASE (Shanghai) Inc.Inventors: Ho-Ming Tong, Teck-Chong Lee, Chao-Fu Weng, Chian-Chi Lin, Che-Ya Chou, Shin-Hua Chao, Song-Fu Yang, Kao-Ming Su
-
Publication number: 20080124836Abstract: A packaging substrate and a manufacturing method thereof are provided. The manufacturing method includes following steps. First, a first packaging substrate including several first substrate units and at least one defected substrate unit is provided. Next, the defected substrate unit is separated from the packaging substrate, and at least one opening is formed in a frame of the first packaging substrate correspondingly. Then, a second substrate unit is provided. The shape of the second substrate unit is different from the shape of the opening. Afterwards, the second substrate unit is disposed in the opening.Type: ApplicationFiled: December 28, 2006Publication date: May 29, 2008Inventors: Ho-Ming Tong, Teck-Chong Lee, Chao-Fu Weng, Chian-Chi Lin, Che-Ya Chou, Shin-Hua Chao, Song-Fu Yang, Kao-Ming Su
-
Publication number: 20080044931Abstract: A packaging substrate and a method of manufacturing the same are provided. The method includes following steps. First, a first substrate including at least one defected packaging unit and several first packaging units is provided. The defected packaging unit and the first packaging units are arranged in an array on the first substrate. Next, the defected packaging unit is removed from the first substrate to correspondingly form at least one opening in the first substrate. Then, a second substrate including at least one second packaging unit is provided. Later, the second packaging unit is separated from the second substrate. The area of the second packaging unit is less than that of the opening. Subsequently, the second packaging unit is disposed in the opening. The edge of the second packaging unit is placed partially against an inner wall of the opening.Type: ApplicationFiled: December 28, 2006Publication date: February 21, 2008Inventors: Ho-Ming Tong, Kao-Ming Su, Chao-Fu Weng, Che-Ya Chou, Shin-Hua Chao, Teck-Chong Lee, Song-Fu Yang, Chian-Chi Lin
-
Publication number: 20070046314Abstract: A process for testing IC wafer is disclosed. Prior to electrically testing chips on a wafer, the wafer is pre-cut to form a plurality of grooves aligned with the scribe lines on the active surface of the wafer. A step of singulating the wafer is performed to form a plurality of individual chips after completing electrical or reliability test of the chips. Due to the pre-cutting step the chips are still integrated on the wafer for accurately probing and testing. And the testing step can obtain the influence of defects between the test terminals and a UBM layer on the function of the chips.Type: ApplicationFiled: October 31, 2006Publication date: March 1, 2007Inventors: Shin-Hua Chao, Yao-Hsin Feng
-
Patent number: 7151317Abstract: A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.Type: GrantFiled: November 9, 2004Date of Patent: December 19, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: Shin-Hua Chao, Jian-Wen Lo
-
Patent number: 7060595Abstract: A circuit substrate includes a board, a plurality of metal layers and an insulator. The board has a plurality of conductive traces layers and a via formed therein. The metal layers are formed on the inner wall of the via and each of the metal layers is electrically connected to its corresponding conductive traces layer. The via is filled with the insulator so that each of the metal layers is electrically isolated from each other. In addition, this invention also provides a fabrication method of the circuit substrate.Type: GrantFiled: July 28, 2003Date of Patent: June 13, 2006Assignee: Advanced Semiconductor Engineering, Inc.Inventors: In-De Ou, Chih-Pin Hung, Chia-Shang Chen, Kuang-Hua Lin, Shin-Hua Chao
-
Publication number: 20060103020Abstract: A circuit structure of a redistribution layer (RDL) is suitable for a chip to define the circuits and the contact window required by the following bump process. The RDL is disposed on the active surface of the chip. The circuit structure of the RDL mainly includes a first titanium layer, a second titanium layer and a conductive layer. Wherein, the conductive layer is made of aluminum; the first titanium layer and the second titanium layer cover the two surfaces of the conductive layer, respectively. The connectivity between the first titanium layer or the second titanium layer and a macromolecule polymer is stronger than the connectivity between the conductive layer and the macromolecule polymer, so that the peeling or crack caused by poor connectivity between the conductive layer and the adjacent dielectric layers are significantly improved thereby.Type: ApplicationFiled: October 31, 2005Publication date: May 18, 2006Inventors: Ho-Ming Tong, Shin-Hua Chao, Chi-Yu Wang, Cherry Mercado Reyes