Abstract: A semiconductor chip package mainly includes a semiconductor chip, a first dielectric layer disposed on the semiconductor chip, a plurality of conductive traces electrically connected to the semiconductor chip, a second dielectric layer disposed on the conductive traces and the first dielectric layer wherein a portion of the conductive traces are exposed from the second dielectric layer, and a plurality of contacts for external connection formed on the exposed portion of the conductive traces. The semiconductor chip has a surface including an active area, a dummy area surrounding the active area, and a plurality of bonding pads disposed on the active area. The bonding pads are electrically connected to the contacts by the conductive traces. The present invention further provides methods for manufacturing the semiconductor chip package.

Abstract: A multi-chip package structure comprising a first chip, a patterned lamination layer, a plurality of first bumps, a second chip and second bumps is provided. The first chip has a first active surface. The patterned lamination layer is disposed on a portion area of the first active surface. The first chip has a plurality of first bonding pads disposed on the first active surface exposed by the patterned lamination layer and the patterned lamination layer has a plurality of second bonding pads disposed thereon. The second chip has a second active surface and the first bumps are disposed on the second active surface. The second chip is electrically connected to the first bonding pads through the first bumps. The second bumps are disposed on the second bonding pads. Moreover, the multi-chip package structure further comprises a component disposed on the first chip and electrically connects to the first bonding pads.

Abstract: An improved method of integrally attaching a heat sink to an IC package for enhancing the thermal conductivity of the package. A heat sink matrix, which is dividable into a plurality of individual heat sinks, is attached to an IC package matrix, which is comprised of a plurality of individual IC packages abutting each other in a matrix arrangement. The IC package matrix and the heat sink matrix attached thereto are then simultaneously cut by means of a machine tool into a plurality of individually formed IC packages each with a heat sink attached; thereby, thermal conductivity of a conventional IC package is enhanced.

Abstract: A process for manufacturing transparent semiconductor packages is disclosed. A wafer having an active surface and a back surface is provided. A plurality of first redistribution lines are formed on the active surface of the wafer to connect the bonding pads of the chips. A transparent polymer is formed over the active surface of the wafer to cover the first redistribution lines. A plurality of first grooves are formed corresponding to the scribe lines and in the back surface of the wafer. Preferably, a back coating is then formed over the back surface to fill the first grooves. Next, a plurality of second grooves are formed corresponding to the first grooves and through the back coating such that the first redistribution lines have exposed portions. A plurality of second redistribution lines on the back coating can extend to the exposed portions of the corresponding first redistribution lines for connecting solder balls on the back surface.

Abstract: A process for testing IC wafer is disclosed. Prior to electrically testing chips on a wafer, the wafer is pre-cut to form a plurality of grooves aligned with the scribe lines on the active surface of the wafer. A step of singulating the wafer is performed to form a plurality of individual chips after completing electrical or reliability test of the chips. Due to the pre-cutting step the chips are still integrated on the wafer for accurately probing and testing.

Abstract: A circuit substrate includes a board, a plurality of metal layers and an insulator. The board has a plurality of conductive traces layers and a via formed therein. The metal layers are formed on the inner wall of the via and each of the metal layers is electrically connected to its corresponding conductive traces layer. The via is filled with the insulator so that each of the metal layers is electrically isolated from each other. In addition, this invention also provides a fabrication method of the circuit substrate.

Abstract: A structure of a heat spreader substrate. A first heat spreader has a first upper surface, a corresponding first lower surface and an opening. A second heat spreader has a second upper surface and a corresponding second lower surface. The second heat spreader is fit tightly into the opening. The second lower surface and the first lower surface are coplanar. A thickness of the second heat spreader is smaller than that of the first heat spreader. A chip is located on the second upper surface. A substrate is located on the first upper surface of the first heat spreader, and the opening is exposed by the substrate.

Abstract: An improved method of integrally attaching a heat sink to an IC package for enhancing the thermal conductivity of the package. A heat sink matrix, which is dividable into a plurality of individual heat sinks, is attached to an IC package matrix, which is comprised of a plurality of individual IC packages abutting each other in a matrix arrangement. The IC package matrix and the heat sink matrix attached thereto are then simultaneously cut by means of a machine tool into a plurality of individually formed IC packages each with a heat sink attached; thereby, thermal conductivity of a conventional IC package is enhanced.

Abstract: A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

Abstract: A heat-spread substrate consisting of a metal heat spreader and a substrate is disclosed. The metal heat spreader has a surface with a cavity, which is adapted for supporting a die. Such surface further includes a ground ring arranged at the periphery of the cavity; a substrate-supporting surface surrounding the periphery of the ground ring; a plurality of first ground pads arranged at the periphery of the substrate-supporting surface; and a plurality of second ground pads arranged on the substrate-supporting surface and protruding it. The substrate is provided on the substrate-supporting surface having a plurality of through holes. The through holes corresponds to the first ground pad so as to make it be located therein, respectively. The substrate further includes a plurality of mounting pads and a plurality of ball pads, in which the mounting pads are close to the cavity, and the first ground pad, the second ground pads and the ball pads are formed in the form of ball grid array and are coplanar roughly.

Abstract: A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

Abstract: A structure of a heat spreader substrate. A first heat spreader has a first upper surface, a corresponding first lower surface and an opening. A second heat spreader has a second upper surface and a corresponding second lower surface. The second heat spreader is fit tightly into the opening. The second lower surface and the first lower surface are coplanar. A thickness of the second heat spreader is smaller than that of the first heat spreader. A chip is located on the second upper surface. A substrate is located on the first upper surface of the first heat spreader, and the opening is exposed by the substrate.

Abstract: A method of making a ball grid array package comprises the steps of: (a) providing a film having an opening defined therein; (b) placing the film on a substrate; (c) attaching a semiconductor chip onto the substrate such that the semiconductor chip is positioned in the opening of the film; (d) electrically coupling the semiconductor chip to the substrate; (e) providing a molding die having a runner, a gate and a molding cavity defined therein, wherein the runner is connected to the molding cavity through the gate; (f) closing and clamping the molding die in a manner that the semiconductor chip is positioned in the molding cavity wherein the edges of the molding cavity fit entirely within the opening of the film and the edges of the runners and the gates are entirely positioned against the film; (g) transferring a hardenable molding compound into the molding cavity; (h) hardening the molding compound; (i) unclamping and opening the molding die; and (j) simultaneously removing the film and degating.

Abstract: A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

Abstract: A ball grid array semiconductor package includes a substrate, a die mounted on the substrate and electrically connected to the substrate by bonding wires, a heat ring mounted on the substrate to surround the die and the bonding wires, and a heat slug mounted on the heat ring to entirely cover the die and the bonding wires thereby providing improved heat dissipation efficiency and overall electrical performance. Encapsulation material is filled into an inner space surrounded by the heat ring, heat slug and substrate to form an encapsulant for protecting the die and bonding wires. The heat ring and heat slug has at least a portion of surface area sequentially coated with a metal medium layer and an insulation layer to enhance the bonding degree between the encapsulant and the heat ring and heat slug.