Abstract: A semiconductor transistor includes a first lightly doped-drain region disposed in a drain region of a semiconductor substrate; a first heavily doped region disposed in the first lightly doped-drain region; and a gate located on the channel region; a gate oxide layer between the gate and the channel region; and a first insulating feature disposed in the first lightly doped-drain region between the channel region and the first heavily doped region. The gate overlaps with the first insulating feature. The thickness of the first insulating feature is greater than that of the gate oxide layer.

Abstract: A structure of a high voltage transistor includes a substrate. A gate insulating layer is disposed on the substrate. A shallow trench isolation structure is formed in the substrate adjacent to the gate insulating layer. The shallow trench isolation structure includes a first sidewall and a second sidewall. A top portion of the first sidewall merges with a side region of the gate insulating layer. A bottom surface of the shallow trench isolation structure is gradually decreasing in depth from the second sidewall to the first sidewall. A source/drain region is formed in the substrate at a side of the gate insulating layer and surrounding the shallow trench isolation structure.

Abstract: A semiconductor transistor includes a first lightly doped-drain region disposed in a drain region of a semiconductor substrate; a first heavily doped region disposed in the first lightly doped-drain region; and a gate located on the channel region; a gate oxide layer between the gate and the channel region; and a first insulating feature disposed in the first lightly doped-drain region between the channel region and the first heavily doped region. The gate overlaps with the first insulating feature. The thickness of the first insulating feature is greater than that of the gate oxide layer.

Abstract: A structure of a high voltage transistor includes a substrate. A gate insulating layer is disposed on the substrate. A shallow trench isolation structure is formed in the substrate adjacent to the gate insulating layer. The shallow trench isolation structure includes a first sidewall and a second sidewall. A top portion of the first sidewall merges with a side region of the gate insulating layer. A bottom surface of the shallow trench isolation structure is gradually decreasing in depth from the second sidewall to the first sidewall. A source/drain region is formed in the substrate at a side of the gate insulating layer and surrounding the shallow trench isolation structure.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a resistive random access memory cell, and a semiconductor element. The resistive random access memory cell is on the substrate. The resistive random access memory cell includes a first electrode having a U shape. The semiconductor element is adjoined with an outer sidewall of the first electrode.

Abstract: A transistor and a method for forming the same are provided. The transistor includes a semiconductor substrate, a gate dielectric layer, a gate electrode, a spacer, and a source/drain. The semiconductor substrate includes a protrusive semiconductor portion protruded from a lower surface of the semiconductor substrate. The gate dielectric layer is on the semiconductor substrate. The gate electrode is on the gate dielectric layer. The spacer is on a sidewall of the gate electrode. An outer surface of the spacer has a concave portion. The source/drain is in the semiconductor substrate.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a resistive random access memory cell, and a semiconductor element. The resistive random access memory cell is on the substrate. The resistive random access memory cell includes a first electrode having a U shape. The semiconductor element is adjoined with an outer sidewall of the first electrode.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a resistive random access memory cell, and a semiconductor element. The resistive random access memory cell is on the substrate. The resistive random access memory cell includes a first electrode having a U shape. The semiconductor element is adjoined with an outer sidewall of the first electrode.

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

Abstract: Method for fabricating semiconductor device, including semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a substrate, a resistive random access memory cell, and a semiconductor element. The resistive random access memory cell is on the substrate. The resistive random access memory cell includes a first electrode having a U shape. The semiconductor element is adjoined with an outer sidewall of the first electrode.

Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A semiconductor device includes semiconductor layer having first device region and second device region. A shallow trench isolation (STI) structure is in the semiconductor layer and located at periphery of the first and second device regions. A first and second insulating layers are on the semiconductor layer and respectively located in the first and second device regions. A first gate structure is located on the first insulating layer. A source region and a drain region are in the semiconductor layer and are located at two sides of the first gate structure. A gate doped region is in a surface region of the semiconductor layer in the second device region to serve as a second gate structure. A channel layer is located on the second insulating layer. A source layer and a drain layer are on the STI structure and are located at two sides of the channel layer.

Abstract: A high voltage transistor including a substrate is provided, and the substrate has an indent region. A doped region is disposed in the substrate at both sides of the indent region. A shallow trench isolation (STI) structure is disposed in the doped region of the substrate, at a periphery region of the indent region, wherein a portion of a bottom of the STI structure within the indent region has a protruding part down into the substrate. A gate insulating layer is disposed on the substrate at a central region of the indent region other than the STI structure, wherein the gate insulating layer has a protruding portion. A gate structure is disposed on the gate insulating layer and the STI structure within the indent region, covering the protruding portion of the gate insulating layer.

Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

Abstract: A semiconductor structure and a manufacturing method of a semiconductor structure are provided. The semiconductor structure includes a semiconductor substrate, a gate, a first diffusion region and a second diffusion region. The gate is disposed on the semiconductor substrate and extends along a first direction. The first diffusion region is formed in the semiconductor substrate, and the second diffusion region is formed in the first diffusion region. The first diffusion region has a first portion located underneath the gate and a second portion protruded from a lateral side of the gate, the first portion has a first length parallel to the first direction, the second portion has a second length parallel to the first direction, and the first length is larger than the second length.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.

Abstract: A semiconductor device and a method of fabricating the same, the semiconductor device includes a substrate, a first gate and a second gate. The first gate is disposed on the substrate and includes a first gate insulating layer, a polysilicon layer, a silicide layer and a protective layer stacked with each other on the substrate and a first spacer surrounds the first gate insulating layer, the polysilicon layer, the silicide layer and the protective layer. The second gate is disposed on the substrate and includes a second gate insulating layer, a work function metal layer and a conductive layer stacked with each other on the substrate, and a second spacer surrounds the second gate insulating layer, the work function metal layer and the conductive layer.