Abstract: A program generating device comprising circuitry configured to: display a schedule screen, in which, for each of a plurality of processes executed in a system including a plurality of industrial devices, at least a name of a process is associated with a variable that is at least either referenced or changed in a process program representing an operation of one or more of the plurality of industrial devices and executed in the process, a plurality of names of the plurality of processes obtained from a process database that is stored as process information are included, and an execution order of the plurality of processes can be specified; receive a specification of the execution order on the schedule screen; and generate a system program based on the execution order and the variable of each process included in the execution order.

Abstract: A semiconductor device is provided that includes a semiconductor substrate containing silicon carbide, and a control circuit unit including one or more control elements and in which the one or more control elements each include a control source region provided in the upper surface of the semiconductor substrate, a control drain region provided in the upper surface of the semiconductor substrate and being of a same conductivity type as the control source region, a control base region provided in contact with the control source region and being of a different conductivity type from the control source region, and a control gate trench section provided from the upper surface of the semiconductor substrate to an internal portion of the semiconductor substrate and being in contact with the control base region.

Abstract: Provided is a semiconductor device which includes: a semiconductor substrate containing silicon carbide; a plurality of first gate trench portions arranged side by side in a first direction; a first mesa portion sandwiched between two of the first gate trench portions; and a mesa facing region not sandwiched between two of the first gate trench portions in the first direction and arranged to face the first mesa portion in a second direction different from the first direction, and in which a contact hole is not provided in an interlayer dielectric film above the first mesa portion, and a source region is provided to extend from the first mesa portion to the mesa facing region and is connected to an upper-surface electrode via the contact hole.

Abstract: Between the front surface of a semiconductor substrate and an n?-type drift region, a p++-type contact region, a p-type base region, a p+-type high-concentration region, and an n-type current spreading region are provided directly beneath a gate pad, sequentially from a front side of the semiconductor substrate so as to face an entire surface of a gate pad, via a field oxide film. The high-concentration region is electrically connected to source electrode wiring via a p++-type wiring region. N+-type regions that are electrically floating (or n+-type wiring regions of the source potential) are selectively provided between the front surface of the semiconductor substrate and the contact region. The n+-type regions have a function of drawing out holes in the high-concentration region and discharging the holes to the source electrode, when the voltage applied to the drain electrode rapidly increases with respect to the potential of the source electrode.

Abstract: A silicon carbide semiconductor device has a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, trenches, gate electrodes provided via a gate insulating film, second semiconductor regions of the second conductivity type underlying the trenches, third semiconductor regions of the second conductivity type between adjacent trenches, a first electrode, and a second electrode. The silicon carbide semiconductor device has an active region end portion, which is free of the first semiconductor regions, and in which the third semiconductor regions are apart from sidewalls of the trenches and are connected to the second semiconductor regions.

Abstract: A semiconductor device has: a silicon carbide semiconductor substrate of a first conductivity type; a first semiconductor layer of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the first conductivity type; a trench; a gate insulating film; a gate electrode; a third semiconductor region of the first conductivity type, and a fourth semiconductor region of the second conductivity type. The third semiconductor region is provided between the gate insulating film on a sidewall of the trench and the first semiconductor region. The fourth semiconductor region is provided between the first semiconductor region and the third semiconductor region, and has an impurity concentration higher than that of the first semiconductor region.

Abstract: A semiconductor device includes a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type; a first semiconductor region of a second conductivity type; a second semiconductor region of the first conductivity type; a trench; a gate insulating film; a gate electrode; a third semiconductor region of the second conductivity type; a fourth semiconductor region of the second conductivity type; a fifth semiconductor region of the first conductivity type, selectively provided in the second semiconductor layer and having an impurity concentration lower than an impurity concentration of the second semiconductor layer; a first electrode; and a second electrode. The fifth semiconductor region has one surface in contact with the first semiconductor region, another surface in contact with the third semiconductor region, and a side surface in contact with the gate insulating film.

Abstract: A silicon carbide semiconductor device includes a silicon carbide semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type, a second semiconductor layer of a second conductivity type, first semiconductor regions of the first conductivity type, second semiconductor regions of the second conductivity type, third semiconductor regions of the second conductivity type, provided in the second semiconductor layer at positions facing the first semiconductor regions in a depth direction and having an impurity concentration higher than an impurity concentration of the second semiconductor layer, trenches, gate insulating films, gate electrodes, a first electrode, a second electrode, and third electrodes. The third electrodes form Schottky junctions with the second semiconductor layer and are provided on the surface of portions of the second semiconductor layer free of the third semiconductor regions.

Abstract: A silicon carbide semiconductor device has an active region and a termination structure portion disposed outside of the active region. The silicon carbide semiconductor device includes a semiconductor substrate of a second conductivity type, a first semiconductor layer of the second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, a gate insulating film, a gate electrode, a first electrode, and a second electrode. During bipolar operation, a smaller density among an electron density and a hole density of an end of the second semiconductor layer in the termination structure portion is at most 1×1015/cm3.

Abstract: A silicon carbide semiconductor device includes first semiconductor areas and second semiconductor areas. The first semiconductor areas have a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, gate electrodes, and first electrodes. The second semiconductor areas have the first semiconductor layer, the second semiconductor layer, third semiconductor regions of the second conductivity type, the gate electrodes, and the first electrodes. The first semiconductor regions include low- impurity-concentration regions and high-impurity-concentration regions. The third semiconductor regions have a potential equal to that of the first electrodes. The first semiconductor regions are connected to the third semiconductor regions by MOS structures.

Abstract: A silicon carbide semiconductor device includes first semiconductor areas and second semiconductor areas. The first semiconductor areas have a first semiconductor layer of a second conductivity type, a second semiconductor layer of a first conductivity type, first semiconductor regions of the second conductivity type, second semiconductor regions of the first conductivity type, gate electrodes, and first electrodes. The second semiconductor areas have the first semiconductor layer, the second semiconductor layer, third semiconductor regions of the second conductivity type, the gate electrodes, and the first electrodes. The first semiconductor regions include low- impurity-concentration regions and high-impurity-concentration regions. The third semiconductor regions have a potential equal to that of the first electrodes. The first semiconductor regions are connected to the third semiconductor regions by MOS structures.

Abstract: A semiconductor device includes an n?-type drift layer of an formed on an n+-type SiC substrate; a p-type layer provided on a surface opposite that facing the n+-type SiC substrate; and an n-type buffer layer provided, as a recombination promoting layer, between the n?-type drift layer and the n+-type SiC substrate, the n-type buffer layer having an impurity concentration higher than that of the n?-type drift layer. In the buffer layer, as a recombination site, a defect energy-level is introduced at a high concentration of 1×1012/cm3 or higher. The buffer layer promotes internal electron-hole recombination and without applying high energy to BPDs at an interface of the buffer layer and the SiC substrate, may reduce the amount of recombination near the interface even at a current density equivalent to that of a conventional structure and thereby, prevents characteristics degradation at the time of operation.

Abstract: For example, a pin diode is constituted by a silicon carbide epitaxial substrate in which silicon carbide epitaxial layers constituting an n-type buffer region, an n?-type drift region, and a p++-type anode region are sequentially formed by epitaxial growth on a front surface of an n+-type silicon carbide substrate. The n?-type drift region has an n-type impurity concentration is, for example, about 1×1014/cm3 to 1×1016/cm3. The n?-type drift region has a boron concentration that is substantially lower than an n-type impurity concentration of the n?-type drift region and that, for example, is about 1×1014/cm3 or less. During epitaxial growth of the n?-type drift region, automatic doping of boron to the n?-type drift region is suppressed, whereby the boron concentration of the n?-type drift region is reduced and the n?-type drift region in which no traps are present is formed.

Abstract: A semiconductor device includes an n?-type drift layer of an formed on an n+-type SiC substrate; a p-type layer provided on a surface opposite that facing the n+-type SiC substrate; and an n-type buffer layer provided, as a recombination promoting layer, between the n?-type drift layer and the n+-type SiC substrate, the n-type buffer layer having an impurity concentration higher than that of the n?-type drift layer. In the buffer layer, as a recombination site, a defect energy-level is introduced at a high concentration of 1×1012/cm3 or higher. The buffer layer promotes internal electron-hole recombination and without applying high energy to BPDs at an interface of the buffer layer and the SiC substrate, may reduce the amount of recombination near the interface even at a current density equivalent to that of a conventional structure and thereby, prevents characteristics degradation at the time of operation.

Abstract: A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements.

Abstract: An edge termination structure that surrounds an active region is disposed outside the active region. In the active region, a MOS gate structure is disposed. Inside an n?-type drift layer, an n-type CS region that becomes a minority carrier barrier is disposed in a surface layer on a p+-type base layer side. The n-type CS region is disposed in the active region and is not disposed in the edge termination structure. Thus, the impurity concentration of the n?-type drift layer inside the edge termination structure is low enough to enable high breakdown voltage to be realized. In the n?-type drift layer, which has a low impurity concentration, a JTE structure that is formed from first and second JTE regions is disposed.

Abstract: A semiconductor device can reduce the number of bonding wires. The semiconductor device includes two or more semiconductor elements each of which has electrodes on a first main surface and a second main surface, an electrode plate that has one surface which is bonded to electrodes on the first main surfaces of the semiconductor elements, with a first bonding material layer interposed therebetween, and extends over the electrodes on the first main surfaces of the two or more semiconductor elements, and a conductive plate that includes a first lead terminal and a semiconductor element bonding portion which is bonded to electrodes on the second main surfaces of the semiconductor elements. A second bonding material layer is interposed therebetween, and is connected to the electrodes on the second main surfaces of the two or more semiconductor elements.

Abstract: A semiconductor device having a low on resistance and high integration level with respect to the surface area of a substrate is provided. In the semiconductor device, a first trench, a second trench, and a third trench are provided in an element formation region provided on a semiconductor substrate. Metal is deposited within the first trench and second trench, to form a drain electrode and a source electrode, respectively. Polysilicon is deposited inside the third trench with a gate insulating film intervening, and a gate electrode is formed.

Abstract: A bidirectional Trench Lateral Power MOSFET (TLPM) can achieve a high breakdown voltage and a low on-resistance. A plurality of straight-shaped islands having circular portions at both ends are surrounded by a trench arrangement. The islands provide first n source regions and a second n source region is formed on the outside of the islands. With such a pattern, the breakdown voltage in the case where the first n source regions are at a high potential can be higher than the breakdown voltage in the case where the second n source region is at a high potential. Alternatively, in the case of not changing the breakdown voltage, the on-resistance can be reduced.

Abstract: ?-Amino hydroxamic acid derivative of the formula I, in which R is C2-C7-alkyl, which is mono-, di- or trisubstituted by halogen, nitro, lower acyloxy, trifluoromethoxy, cyano, C3-C5-cycloalkyl or unsubstituted or substituted C3-C6-heteroaryl comprising one or two heteroatoms selected from the group consisting of O, S and N; or C3-C7-alkenyl or C3-C7-alkynyl, which in each case is unsubstituted or mono-, di- or trisubstituted by halogen, nitro, lower acyloxy, trifluoromethoxy, cyano, C3-C5-cycloalkyl or unsubstituted or substituted C3-C6-heteroaryl comprising one or two heteroatoms selected from the group consisting of O, S and N; and the other symbols are as defined in claim 1, are described. These compounds are MMP and in particular MMP2 inhibitors and can be used for treatment of MMP dependent diseases, in particular inflammation conditions, rheumatoid arthritis, osteoarthritis, tumors (tumor growth, metastasis, progression or invasion) and pulmonary disorders (e.g. emphysema, COPD).