Patents by Inventor Shinichiro Taguchi
Shinichiro Taguchi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220214563Abstract: A spectacle lens design system capable of suppressing deformation during finishing processing.Type: ApplicationFiled: August 21, 2020Publication date: July 7, 2022Applicant: HOYA LENS THAILAND LTD.Inventors: Shinichiro TAGUCHI, Takao TANAKA, Keima SAKATA, Tadashi KAGA
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Publication number: 20200409174Abstract: A spectacle lens design system includes: an information acquisition device; a first design data deriving device deriving first design data of an eyeball-side surface; a first thickness information deriving device deriving first values of wall thickness and edge thickness of the spectacle lens; a second design data deriving device deriving second design data of the eyeball-side surface, which has higher accuracy than the first design data, based on the prescription value of the wearer and the design data of the object-side surface; and a second thickness information deriving device deriving second values of the wall thickness and edge thickness of the spectacle lens based on the derived second design data of the eyeball-side surface, the design data of the object-side surface, and the minimum wall thickness and minimum edge thickness information of the spectacle lens.Type: ApplicationFiled: September 16, 2020Publication date: December 31, 2020Applicant: HOYA LENS THAILAND LTD.Inventors: Shinichiro TAGUCHI, Takao TANAKA
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Patent number: 9178226Abstract: A fuel cell sealing structure has a power generating body, and first and second separators arranged in both sides in a thickness direction of the power generating body. On a surface in one side in a thickness direction of the first separator, formed integrally first and second sealing protrusions respectively brought into close contact with an outer peripheral portion of the power generating body and the second separator in an outer peripheral side of the first sealing protrusion, and a short circuit prevention rib protruding in line with the first and second sealing protrusions by an electrically insulating rubber-like elastic material. On a surface in another side thereof, formed integrally a third sealing protrusion brought into close contact with a surface in an opposite side to the power generating body in the second separator, by the electrically insulating rubber-like elastic material.Type: GrantFiled: May 27, 2010Date of Patent: November 3, 2015Assignee: NOK CorporationInventors: Takeshi Masaka, Yoshihiro Kurano, Shinichiro Taguchi, Kenichi Kikuchi, Tetsuya Urakawa
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Patent number: 8927174Abstract: A sealing structure of a fuel cell has a first gasket made of an elastomer and provided integrally on a separator, and a second gasket made of an elastomer and provided integrally on other separator. A membrane-electrode assembly is sandwiched or pinched by the first and second gaskets. The first gasket has a main lip in which a top portion brought into close contact with the membrane-electrode assembly is formed flat. The second gasket has a flat seal portion and a sub lip protruding from this flat seal portion at a position opposing the main lip. The flat seal portion and the sub lip are brought into close contact with the membrane-electrode assembly. The width of the top portion of the main lip is narrower than the width of the flat seal portion, and larger than the width of the sub lip.Type: GrantFiled: April 27, 2010Date of Patent: January 6, 2015Assignee: NOK CorporationInventors: Shinichiro Taguchi, Shigeru Watanabe
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Publication number: 20120107718Abstract: A fuel cell sealing structure has a power generating body, and first and second separators arranged in both sides in a thickness direction of the power generating body. On a surface in one side in a thickness direction of the first separator, formed integrally first and second sealing protrusions respectively brought into close contact with an outer peripheral portion of the power generating body and the second separator in an outer peripheral side of the first sealing protrusion, and a short circuit prevention rib protruding in line with the first and second sealing protrusions by an electrically insulating rubber-like elastic material. On a surface in another side thereof, formed integrally a third sealing protrusion brought into close contact with a surface in an opposite side to the power generating body in the second separator, by the electrically insulating rubber-like elastic material.Type: ApplicationFiled: May 27, 2010Publication date: May 3, 2012Applicant: NOK CORPORATIONInventors: Takeshi Masaka, Yoshihiro Kurano, Shinichiro Taguchi, Kenichi Kikuchi, Tetsuya Urakawa
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Publication number: 20120064429Abstract: A sealing structure of a fuel cell has a first gasket made of an elastomer and provided integrally on a separator, and a second gasket made of an elastomer and provided integrally on other separator. A membrane-electrode assembly is sandwiched or pinched by the first and second gaskets. The first gasket has a main lip in which a top portion brought into close contact with the membrane-electrode assembly is formed flat. The second gasket has a flat seal portion and a sub lip protruding from this flat seal portion at a position opposing the main lip. The flat seal portion and the sub lip are brought into close contact with the membrane-electrode assembly. The width of the top portion of the main lip is narrower than the width of the flat seal portion, and larger than the width of the sub lip.Type: ApplicationFiled: April 27, 2010Publication date: March 15, 2012Applicant: NOK CORPORATIONInventors: Shinichiro Taguchi, Shigeru Watanabe
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Patent number: 7571260Abstract: A microcomputer includes a CPU, multiple resources, and an output circuit having an address decoder. The CPU outputs an address signal to the address decoder. The address decoder decodes the address signal and the output circuit outputs a select signal to at least one of the resources in accordance with the decoded address signal. Each of the resources is writable by the CPU when receiving the select signal. When the address signal indicates a predetermined address, the output circuit outputs the select signal to at least two of the resources at a time. Thus, data can be written to the multiple resources at a time. Therefore, the CPU can write the data to the multiple resources within a reduced time by using the output circuit.Type: GrantFiled: October 3, 2006Date of Patent: August 4, 2009Assignee: DENSO CORPORATIONInventors: Shinichiro Taguchi, Kenji Yamada, Hideaki Ishihara
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Publication number: 20090140498Abstract: To avoid strict control of flatness of a pressing portion, while keeping stability, in a sealing device comprising a metal ring and a seal portion, a metal ring (2) has an annular pressing portion (5) provided with a predetermined width in a diametrical direction for pressing an opponent member (11) when the metal ring (2) shifts in the axial direction, pressing surface (7) of the pressing portion (5) is formed in a circular arc or wavy sectional shape protruding toward the opponent member (11), the pressing portion (5) is constituted by an outward flange portion (6) integrally formed at an end of a tubular portion (4) of the metal ring (2), and the flange portion (6) has a smaller thickness than the tubular portion (4) and is formed in a circular arc or wavy sectional shape so as to have a spring characteristic.Type: ApplicationFiled: October 18, 2006Publication date: June 4, 2009Applicant: NOK CORPORATIONInventors: Shinichiro Taguchi, Yoshiyuki Kanzaki, Kiichiro Goto
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Patent number: 7356721Abstract: A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.Type: GrantFiled: December 9, 2004Date of Patent: April 8, 2008Assignee: DENSO CORPORATIONInventors: Shinichiro Taguchi, Hideaki Ishihara, Yoshinori Teshima, Naoki Ito
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Publication number: 20080023893Abstract: In a hermetically sealing device provided by fitting and mounting a seal member on an annular member, fitting strength between the annular member and the seal member is reduced. A seal member (7) is provided with a reinforcing ring (7b), a contact part (72), which is integrally provided with the reinforcing ring (7b) and contacts a first outer circumference skirt part (13a) when it is fitted in the first outer circumference skirt part (13a) of a piston member (11), and a seal main body (7a) which has a seal lip (71) which hermetically contacts a circumference plane of a piston inserting hole (5).Type: ApplicationFiled: March 11, 2005Publication date: January 31, 2008Applicant: NOK CORPORATIONInventors: Yasunari Hamaya, Shinichiro Taguchi, Yoshiyuki Kanzaki, Kiichiro Goto
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Publication number: 20070158180Abstract: The present invention provides a magnetron sputtering method and a magnetron sputtering apparatus that can significantly reduce a non-erosion region causing an abnormal electrical discharge on a surface of a target and deposition of target materials. A plurality of targets 8A, 8B, 8C and 8D are disposed in a vacuum atmosphere while being electrically independent to each other; and sputtering is performed by generating magnetron discharge in the vicinity of the targets 8A, 8B, 8C and 8D. During the sputtering, voltages having a phase difference of 180 degrees are alternately applied to the adjacent targets 8A, 8B, 8C and 8D at a predetermined timing.Type: ApplicationFiled: November 30, 2006Publication date: July 12, 2007Applicant: ULVAC, Inc.Inventors: Atsushi Ota, Shinichiro Taguchi, Isao Sugiura, Noriaki Tani, Makoto Arai, Junya Kiyota
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Publication number: 20070076518Abstract: A microcomputer includes a CPU, multiple resources, and an output circuit having an address decoder. The CPU outputs an address signal to the address decoder. The address decoder decodes the address signal and the output circuit outputs a select signal to at least one of the resources in accordance with the decoded address signal. Each of the resources is writable by the CPU when receiving the select signal. When the address signal indicates a predetermined address, the output circuit outputs the select signal to at least two of the resources at a time. Thus, data can be written to the multiple resources at a time. Therefore, the CPU can write the data to the multiple resources within a reduced time by using the output circuit.Type: ApplicationFiled: October 3, 2006Publication date: April 5, 2007Applicant: DENSO CORPORATIONInventors: Shinichiro Taguchi, Kenji Yamada, Hideaki Ishihara
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Publication number: 20050188131Abstract: A single-chip microcomputer includes a logic circuit, a CPU and a flip-flop for synchronizing an interrupt-request signal, which is supplied by the logic circuit to the CPU, based on a clock signal. A multi-chip emulation apparatus comprises a peripheral evaluation chip, a CPU evaluation chip and a device, which are used for emulating functions of the logic circuit, the CPU and the flip-flop respectively. When the multi-chip emulation apparatus is used for emulating functions of the single-chip microcomputer in the development, the device for emulating functions of the flip-flop synchronizes the interrupt-request signal to absorb a delay time incurred by the interrupt-request signal due to a physical distance between the peripheral evaluation chip and the CPU evaluation chip so that an interrupt-handling timing in the emulation matches an interrupt-handling timing in the real operation of the single-chip microcomputer.Type: ApplicationFiled: December 9, 2004Publication date: August 25, 2005Inventors: Shinichiro Taguchi, Hideaki Ishihara, Yoshinori Teshima, Naoki Ito
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Patent number: 6222621Abstract: The optimum optical properties of a spectacle lens that correspond with the state in which the spectacle lens is worn by respective wearers are found and evaluated. Three-dimensional shape data of the spectacle lens comprising the determinations of a three-dimensional determination device that determines the surface shape f the spectacle lens, parameters of the state in which the spectacle lens is worn, such as the distance from the center of rotation, and material parameters, such as the refractive index of the spectacle lens, are input to a computer that calculates optical properties of a spectacle lens.Type: GrantFiled: October 8, 1999Date of Patent: April 24, 2001Assignee: Hoyo CorporationInventor: Shinichiro Taguchi
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Patent number: 4500931Abstract: Signal sampling transistors, to which signals to be sampled are coupled under the control of a first gate signal, and which couples these signals to holds circuits according to the first gate signal, are provided. A switching circuit for differentially switching the signal sampling transistors to complementarily turn off one of these transistors is also provided. This switching circuit includes transistors, one of which is turned on while the other is turned off according to a second gate signal. The individual switching circuit transistors are connected to the respective sampling transistors. With this arrangement, of the sampling transistors one to which the "on" state one of the switching circuit transistors is connected is turned off while the other is turned on. Thus, the conduction state of the sampling transistors for coupling the aforementioned signals to be sampled to the hold circuits can be forcibly controlled by the second gate signal irrespective of the first gate signal.Type: GrantFiled: December 12, 1983Date of Patent: February 19, 1985Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Shinichiro Taguchi, Nobuya Nagao, Yutaka Ogihara
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Patent number: 4456838Abstract: An output circuit and a biasing circuit for biasing an oscillation circuit comprise a current mirror circuit. The DC level of the output signal from the oscillation circuit is level shifted by controlling the current of the current mirror circuit comprising the biasing circuit and the output circuit. This control is performed by suitably determining the number of diodes and the resistances of the resistors making up the current mirror circuit. The biasing circuit of the oscillation circuit may thus be utilized as the level shifting circuit, the DC level of the output signal of the oscillation circuit may be set to a predetermined level, and fluctuations in the duty ratio of the oscillation output may be suppressed.Type: GrantFiled: February 25, 1981Date of Patent: June 26, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Shinichiro Taguchi, Nobuya Nagao, Yutaka Ogihara
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Patent number: 4435657Abstract: Horizontal sync signal is applied as a reference pulse signal to a first input terminal of a phase detector and is also applied as a gating pulse to a gate circuit. Output of a frequency divider which divides the frequency of the output of a VCO is applied as a comparison pulse to a second input terminal of the phase detector. In the phase detector, a phase detection pulse having a pulse width proportional to the phase difference between the reference pulse and the comparison pulse is obtained. This phase detection pulse is applied through a buffer to a gate circuit. In the gate circuit, the current path from the phase detection pulse input terminal to the output terminal is held conductive during the period of the gating pulse, and during this period an output pulse containing as a component thereof the phase detection pulse mentioned above is obtained. This output pulse is smoothed through a filter to be applied as an oscillation frequency control voltage input to the VCO.Type: GrantFiled: February 27, 1981Date of Patent: March 6, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Shinichiro Taguchi, Nobuya Nagao, Yutaka Ogihara
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Patent number: 4433255Abstract: Signal sampling transistors, to which signals to be sampled are coupled under the control of a first gate signal, and which couples these signals to holds circuits according to the first gate signal, are provided. A switching circuit for differentially switching the signal sampling transistors to complementarily turn off one of these transistors is also provided. This switching circuit includes transistors, one of which is turned on while the other is turned off according to a second gate signal. The individual switching circuit transistors are connected to the respective sampling transistors. With this arrangement, of the sampling transistors one to which the "on" state one of the switching circuit transistors is connected is turned off while the other is turned on. Thus, the conduction state of the sampling transistors for coupling the aforementioned signals to be sampled to the hold circuits can be forcibly controlled by the second gate signal irrespective of the first gate signal.Type: GrantFiled: February 25, 1981Date of Patent: February 21, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Shinichiro Taguchi, Nobuya Nagao, Yutaka Ogihara
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Patent number: 4430674Abstract: DC control signals responsive to ACC voltages are applied to a color signal amplifier, to which recording and reproducing color signals are applied, to control the operation of the color signal amplifier to recording or reproducing mode. Such control is attained by using color killer signal responsive to mode changeover and ACC detector signals which serve to assign the color signal amplifier to recording or reproducing mode. Color signals are obtained from the output terminal of the color signal amplifier in both modes. In the case of recording mode, essentially undesirable recording color signals appearing to the output terminal of the color signal amplifier are by-passed by a low-pass filter, and only ACC detector voltages which are used as color killer signals are supplied to a mixer circuit which mixes brightness and color signals to generate composite color signals to be recorded.Type: GrantFiled: February 25, 1981Date of Patent: February 7, 1984Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Shinichiro Taguchi, Nobuya Nagao, Yutaka Ogihara
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Patent number: 4405901Abstract: An arrangement for coupling an AC input signal having a DC component to a plurality of differential amplifiers without causing a DC off-set. The AC input including a DC component is commonly fed through a compensation resistor to a signal input terminal of each of the differential amplifiers. The DC component contained in the AC input signal is extracted by a low-pass filter including a resistor and a capacitor and is applied to a bias input terminal of each of the differential amplifiers.Type: GrantFiled: February 23, 1981Date of Patent: September 20, 1983Assignee: Tokyo Shibaura Denki Kabushiki KaishaInventors: Shinichiro Taguchi, Nobuya Nagao, Yutaka Ogihara