Patents by Inventor Shin-Jang Shen

Shin-Jang Shen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110069571
    Abstract: One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.
    Type: Application
    Filed: June 16, 2010
    Publication date: March 24, 2011
    Applicant: Macronix International Co., Ltd.
    Inventors: Shin-Jang Shen, Bo-Chang Wu, Chuan Ying Yu, Ken-Hui Chen, Kuen-Long Chang, Chun-Hsiung Hung
  • Patent number: 7324402
    Abstract: A flash memory includes: a plurality of switches; a global bit line; and a plurality of memory blocks, each containing a plurality of local bit lines, and a plurality of memory units coupled to the plurality of local bit lines respectively. A first switch couples a first local bit line to the global bit line; a second switch couples a second local bit line to the global bit line; a third switch couples the first local bit line to a first voltage source; and a fourth switch couples the second local bit line to a second voltage source.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: January 29, 2008
    Assignee: Skymedi Corporation
    Inventors: Hsin-Chien Chen, Shin-Jang Shen, Fu-Chia Shone
  • Patent number: 7313029
    Abstract: A method for erasing data of a flash memory is disclosed. The flash memory includes a plurality of memory cells coupled to a word line, where each of the memory cells has a substrate, an isolated carrier storage layer, and a control gate coupled to the word line. And the method includes: coupling the substrate to a first voltage to increase a voltage level of the substrate; before erasing data, floating the control gate to make a voltage level of the control gate increase with the voltage level of the substrate; and coupling the control gate to a second voltage via the word line to discharge charges on the isolated carrier storage layer for erasing data.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: December 25, 2007
    Assignee: Skymedi Corporation
    Inventors: Shin-Jang Shen, Fu-Chia Shone
  • Publication number: 20070242525
    Abstract: A method for erasing data of a flash memory is disclosed. The flash memory includes a plurality of memory cells coupled to a word line, where each of the memory cells has a substrate, an isolated carrier storage layer, and a control gate coupled to the word line. And the method includes: coupling the substrate to a first voltage to increase a voltage level of the substrate; before erasing data, floating the control gate to make a voltage level of the control gate increase with the voltage level of the substrate; and coupling the control gate to a second voltage via the word line to discharge charges on the isolated carrier storage layer for erasing data.
    Type: Application
    Filed: April 7, 2006
    Publication date: October 18, 2007
    Inventors: Shin-Jang Shen, Fu-Chia Shone
  • Patent number: 6930926
    Abstract: A method for erasing a flash EEPROM. The flash EEROM includes a number of memory units. First, the flash EEPROM is pre-programmed. Second, the step of erasing the flash EEPROM is performed and the flash EEPROM is then soft-programmed. Subsequently, the final step is performed to determine if the erasing step succeeds.
    Type: Grant
    Filed: January 30, 2003
    Date of Patent: August 16, 2005
    Assignee: Macronix International Co., Ltd.
    Inventors: Yu-Shen Lin, Shin-Jang Shen, Chun-Hsiung Hung, Ho-Chun Liou, Shuo-Nan Hung
  • Publication number: 20030161187
    Abstract: A method for erasing a flash EEPROM. The flash EEROM includes a number of memory units. First, the flash EEPROM is pre-programmed. Second, the step of erasing the flash EEPROM is performed and the flash EEPROM is then soft-programmed. Subsequently, the final step is performed to determine if the erasing step succeeds.
    Type: Application
    Filed: January 30, 2003
    Publication date: August 28, 2003
    Inventors: Yu-Shen Lin, Shin-Jang Shen, Chun-Hsiung Hung, Ho-Chun Liou, Shuo-Nan Hung