Abstract: Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.

Abstract: A semiconductor package including a lid having one or more heat pipes located on and/or within the lid to provide improved thermal management. A lid for a semiconductor package having one or more heat pipes thermally integrated with the lid may provide more uniform heat loss from the semiconductor package, reduce the risk of damage to the package due to excessive heat accumulation, and may enable the lid to be fabricated using less expensive materials, thereby reducing the costs of a semiconductor package.

Abstract: A package includes a package substrate, the package substrate having a first side and a second side opposite to the first side, a package component bonded to the first side of the package substrate, a front-side warpage control structure attached to the first side of the package substrate, and a backside warpage control structure embedded in the package substrate from the second side of the package substrate. The front-side warpage control structure includes a first disconnected structure and a second disconnected structure laterally separated from each other by a gap. The backside warpage control structure includes a third disconnected structure and a fourth disconnected structure laterally separated from each other.

Abstract: First redistribution interconnect structures having a respective uniform thickness throughout are formed on a top surface of a first adhesive layer over a first carrier wafer. Redistribution dielectric layers and additional redistribution interconnect structures are formed over the first redistribution interconnect structures to provide at least one redistribution structure. A respective set of one or more semiconductor dies is attached to each of the at least one redistribution structure. The first redistribution interconnect structures are physically exposed by removing the first carrier wafer and the first adhesive layer. Fan-out bump structures are formed on the physically exposed first planar surfaces of the first redistribution interconnect structures.

Abstract: In an embodiment, a package including: a redistribution structure including a first dielectric layer and a first conductive element disposed in the first dielectric layer; a first semiconductor device bonded to the redistribution structure, wherein the first semiconductor device includes a first corner; and an underfill disposed over the redistribution structure and including a first protrusion extending into the first dielectric layer of the redistribution structure, wherein the first protrusion of the underfill overlaps the first corner of the first semiconductor device in a plan view.

Abstract: A semiconductor package is fabricated by attaching a first component to a second component. The first component is assembled by forming a first redistribution structure over a substrate. A through via is then formed over the first redistribution structure, and a die is attached to the first redistribution structure active-side down. The second component includes a second redistribution structure, which is then attached to the through via. A molding compound is deposited between the first redistribution structure and the second redistribution structure and further around the sides of the second component.

Abstract: A method includes forming a redistribution structure including metallization patterns; attaching a semiconductor device to a first side of the redistribution structure; encapsulating the semiconductor device with a first encapsulant; forming openings in the first encapsulant, the openings exposing a metallization pattern of the redistribution structure; forming a conductive material in the openings, comprising at least partially filling the openings with a conductive paste; after forming the conductive material, attaching integrated devices to a second side of the redistribution structure; encapsulating the integrated devices with a second encapsulant; and after encapsulating the integrated devices, forming a pre-solder material on the conductive material.

Abstract: A semiconductor structure includes a packaging substrate containing at least one trench located between a first region and a second region, a first chip module bonded to the first region of the packaging substrate through first solder material portions, and a second chip module bonded to the second region of the packaging substrate through second solder material portions. A first underfill material portion laterally surrounds the first solder material portions and extends into a first portion of the at least one trench. A second underfill material portion laterally surrounds the second solder material portions and extends into a second portion of the at least one trench. The at least one trench is used to absorb stress to the underfill material portions.

Abstract: Semiconductor packages and methods of fabricating semiconductor packages include bonding structures on a surface of an interposer having non-uniform height dimensions in different regions of the interposer. A plurality of solder connections may contact the pillars and electrically connect the respective pillars of the interposer to corresponding bonding structures on a package substrate. The variation in the heights of the pillars in different regions of the interposer may compensate for warping of the interposer and improve the reliability of the electrical connections between the interposer and the package substrate.

Abstract: A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least a circuit substrate, a semiconductor die and a filling material. The circuit substrate has a first surface, a second surface opposite to the first surface and a cavity concave from the first surface. The circuit substrate includes a dielectric material and a metal floor plate embedded in the dielectric material and located below the cavity. A location of the metal floor plate corresponds to a location of the cavity. The metal floor plate is electrically floating and isolated by the dielectric material. The semiconductor die is disposed in the cavity and electrically connected with the circuit substrate. The filling material is disposed between the semiconductor die and the circuit substrate. The filling material fills the cavity and encapsulates the semiconductor die to attach the semiconductor die and the circuit substrate.

Abstract: A semiconductor device includes a circuit substrate, at least one semiconductor die, a first frame, and a second frame. The at least one semiconductor die is connected to the circuit substrate. The first frame is disposed on the circuit substrate and encircles the at least one semiconductor die. The second frame is stacked on the first frame. The first frame includes a base portion and an overhang portion. The base portion has a first width. The overhang portion is disposed on the base portion and has a second width greater than the first width. The overhang portion laterally protrudes towards the at least one semiconductor die with respect to the base portion. The first width and the second width are measured in a protruding direction of the overhang portion.

Abstract: Embodiments of the present disclosure include a semiconductor device and methods of forming a semiconductor device. An embodiment is a semiconductor device comprising an interconnecting structure consisting of a plurality of thin film layers and a plurality of metal layers disposed therein, each of the plurality of metal layers having substantially a same top surface area, and a die comprising an active surface and a backside surface opposite the active surface, the active surface being directly coupled to a first side of the interconnecting structure. The semiconductor device further comprises a first connector directly coupled to a second side of the interconnecting structure, the second side being opposite the first side.

Abstract: A package structure is provided. The package structure includes a first package component and a second package component. The second package component includes a substrate and an electronic component disposed on the substrate, and the first package component is mounted to the substrate. The package structure further includes a ring structure disposed on the second package component and around the first package component. The ring structure has a first foot and a second foot, the first foot and the second foot extend toward the substrate, the electronic component is covered by the ring structure and located between the first foot and the second foot, and the first package component is exposed from the ring structure.

Abstract: A metallization structure electrically connected to a conductive bump is provided. The metallization structure includes an oblong-shaped or elliptical-shaped redistribution pad, a conductive via disposed on the oblong-shaped or elliptical-shaped redistribution pad, and an under bump metallurgy covering the conductive via, wherein the conductive bump is disposed on the UBM. Furthermore, a package structure including the above-mentioned metallization structures is provided.

Abstract: A metallization structure electrically connected to a conductive bump is provided. The metallization structure includes an oblong-shaped or elliptical-shaped redistribution pad, a conductive via disposed on the oblong-shaped or elliptical-shaped redistribution pad, and an under bump metallurgy covering the conductive via, wherein the conductive bump is disposed on the UBM. Furthermore, a package structure including the above-mentioned metallization structures is provided.

Abstract: A semiconductor package is provided. The semiconductor package includes a redistribution structure, a semiconductor die, and an interposer structure. The interposer structure includes an insulating base having a first surface facing the semiconductor die and a second surface opposite to the first surface and conductive features formed over the insulating base. The conductive features include first portions on the first surface of the insulating base and vertically overlapping the semiconductor die, second portions on the first surface of the insulating base and located outside a projection area of the semiconductor die in a top view, third portions on the second surface of the insulating base and vertically overlapping the semiconductor die, and fourth portions on the second surface of the insulating base and located outside the projection area of the semiconductor die in the top view. The interposer structure includes capping layers and dielectric features.

Abstract: A fan-out package includes a redistribution structure having redistribution-side bonding structures, a plurality of semiconductor dies including a respective set of die-side bonding structures that is attached to a respective subset of the redistribution-side bonding structures through a respective set of solder material portions, and an underfill material portion laterally surrounding the redistribution-side bonding structures and the die-side bonding structures of the plurality of semiconductor dies. A subset of the redistribution-side bonding structures is not bonded to any of the die-side bonding structures of the plurality of semiconductor dies and is laterally surrounded by the underfill material portion, and is used to provide uniform distribution of the underfill material during formation of the underfill material portion.

Abstract: A package structure includes a circuit substrate, a semiconductor package, a thermal interface material, a lid structure and a heat dissipation structure. The semiconductor package is disposed on and electrically connected to the circuit substrate. The thermal interface material is disposed on the semiconductor package. The lid structure is disposed on the circuit substrate and surrounding the semiconductor package, wherein the lid structure comprises a supporting part that is partially covering and in physical contact with the thermal interface material. The heat dissipation structure is disposed on the lid structure and in physical contact with the supporting part of the lid structure.

Abstract: A package structure includes a redistribution structure, a first semiconductor die, a first passive component, a second semiconductor die, a first insulating encapsulant, a second insulating encapsulant, a second passive component and a global shielding structure. The redistribution structure includes dielectric layers and conductive layers alternately stacked. The first semiconductor die, the first passive component and the second semiconductor die are disposed on a first surface of the redistribution structure. The first insulating encapsulant is encapsulating the first semiconductor die and the first passive component. The second insulating encapsulant is encapsulating the second semiconductor die, wherein the second insulating encapsulant is separated from the first insulating encapsulant. The second passive component is disposed on a second surface of the redistribution structure.

Abstract: Some implementations herein describe a semiconductor package. The semiconductor package, which may correspond to a high-performance computing semiconductor package, includes an interposer. The interposer includes tapered interconnect structures formed using a laser plug process. The tapered interconnect structures may include a length that is lesser relative to a length of the column-shaped interconnect structures formed using a through-silicon via process. Such a length reduces a thickness of the interposer and reduces a length of electrical connections through the interposer. In this way, a signal integrity may be increased and parasitics of the semiconductor package including the tapered interconnect structures may be reduced to increase a performance of the semiconductor package. Additionally, the reduced thickness of the interposer may reduce an overall thickness of the semiconductor package to save space consumed by the semiconductor package in a computing system.