Patents by Inventor Shin-Puu Jeng
Shin-Puu Jeng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11862580Abstract: A semiconductor package provided herein includes a wiring substrate, a semiconductor component, conductor terminals, a bottom stiffener and a top stiffener. The wiring substrate has a first surface and a second surface opposite to the first surface. The semiconductor component is disposed on the first surface of the wiring substrate. The conductor terminals are disposed on the second surface of the wiring substrate and electrically connected to the semiconductor component through the wiring substrate. The bottom stiffener is disposed on the second surface of the wiring substrate and positioned between the conductor terminals. The top stiffener is disposed on the first surface of the wiring substrate. The top stiffener is laterally spaced further away from the semiconductor component than the bottom stiffener.Type: GrantFiled: July 27, 2022Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chin-Hua Wang, Shu-Shen Yeh, Yu-Sheng Lin, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11862549Abstract: A semiconductor package includes a die, a redistribution structure and a plurality of conductive terminals. The redistribution structure is disposed below and electrically connected to the die. The redistribution structure includes a plurality of conductive patterns, and at least one of the plurality of conductive patterns has a cross-section substantially parallel to the surface of the die. The cross-section has a long-axis and a short-axis, and the long-axis intersects with a center axis of the die. The conductive terminals are disposed below and electrically connected to the redistribution structure.Type: GrantFiled: August 27, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Po-Chen Lai, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11862606Abstract: A package includes a corner, a device die, a plurality of redistribution lines underlying the device die, and a plurality of metal pads electrically coupled to the plurality of redistribution lines. The plurality of metal pads includes a corner metal pad closest to the corner, wherein the corner metal pad is a center-facing pad having a bird-beak direction substantially pointing to a center of the package. The plurality of metal pads further includes a metal pad farther away from the corner than the corner metal pad, wherein the metal pad is a non-center-facing pad having a bird-beak direction pointing away from the center of the package.Type: GrantFiled: June 29, 2021Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Shin-Puu Jeng, Der-Chyang Yeh, Hsien-Wei Chen, Jie Chen
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Patent number: 11862469Abstract: A method of forming a package structure includes the following steps. A first package structure is formed. The first package structure is connected to a second package structure. The method of forming the first package structure includes the following steps. A redistribution layer (RDL) structure is formed. A die is bonded to the RDL structure. The RDL structure is electrically connected to the die. A through via is formed on the RDL structure and laterally aside the die. An encapsulant is formed to laterally encapsulate the through via and the die. A protection layer is formed over the encapsulant and the die. A cap is formed on the through via and laterally aside the protection layer, wherein the cap has a top surface higher than a top surface of the encapsulant and lower than a top surface of the protection layer. The cap is removed from the first package structure.Type: GrantFiled: March 31, 2022Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Feng-Cheng Hsu, Shuo-Mao Chen, Shin-Puu Jeng
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Publication number: 20230420314Abstract: A bonded assembly includes an interposer including redistribution wiring interconnects and redistribution insulating layers and including recesses in corner regions. The recesses include surfaces that are recessed relative to a horizontal plane including a horizontal surface of the interposer. A least one semiconductor die is attached to the interposer through a respective array of solder material portions. An underfill material portion is located between the interposer and the at least one semiconductor die. The underfill material includes downward-protruding anchor portions that protrude downward from a horizontally-extending portion of the underfill material portion that laterally surrounds each array of solder material portions into the recesses.Type: ApplicationFiled: June 27, 2022Publication date: December 28, 2023Inventors: Chin-Hua Wang, Yu-Fan Chen, Yu Chen Lee, Shin-Puu Jeng
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Patent number: 11854929Abstract: An semiconductor package includes a redistribution structure, a first semiconductor device, a second semiconductor device, an underfill layer and an encapsulant. The first semiconductor device is disposed on and electrically connected with the redistribution structure, wherein the first semiconductor device has a first bottom surface, a first top surface and a first side surface connecting with the first bottom surface and the first top surface, the first side surface comprises a first sub-surface and a second sub-surface connected with each other, the first sub-surface is connected with the first bottom surface, and a first obtuse angle is between the first sub-surface and the second sub-surface.Type: GrantFiled: August 30, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Sheng Lin, Chin-Hua Wang, Shu-Shen Yeh, Chien-Hung Chen, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11855008Abstract: A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.Type: GrantFiled: August 10, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shu-Shen Yeh, Che-Chia Yang, Chin-Hua Wang, Po-Yao Lin, Shin-Puu Jeng, Chia-Hsiang Lin
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Patent number: 11854837Abstract: Semiconductor devices and methods of manufactured are presented in which a first redistribution structure is formed, semiconductor devices are bonded to the first redistribution structure, and the semiconductor devices are encapsulated in an encapsulant. First openings are formed within the encapsulant, such as along corners of the encapsulant, in order to help relieve stress and reduce cracks.Type: GrantFiled: June 14, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Po-Chen Lai, Ming-Chih Yew, Po-Yao Lin, Chien-Sheng Chen, Shin-Puu Jeng
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Patent number: 11854956Abstract: A semiconductor die package is provided. The semiconductor die package includes a semiconductor die and a package substrate disposed below the semiconductor die. The semiconductor die has a corner. The package substrate includes several conductive lines, and one of the conductive lines under the corner of the semiconductor die includes a first line segment and a second line segment. The first and second line segments are connected together, and the second line segment has a smaller line width than the first line segment. The first line segment is linear and extends in a first direction. The second line segment is non-linear and has a varying extension direction.Type: GrantFiled: July 16, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ya-Huei Lee, Shu-Shen Yeh, Kuo-Ching Hsu, Shyue-Ter Leu, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11855066Abstract: A method of manufacturing a semiconductor structure forming a redistribution layer (RDL); forming a conductive pad over the RDL; performing a first electrical test through the conductive pad; bonding a first die over the RDL by a connector; disposing a first underfill material to surround the connector; performing a second electrical test through the conductive pad; disposing a second die over the first die and the conductive pad; and disposing a second underfill material to surround the second die, wherein the conductive pad is at least partially in contact with the second underfill material, and is protruded from the RDL during the first electrical test and the second electrical test.Type: GrantFiled: May 13, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Hsiang-Tai Lu, Shuo-Mao Chen, Mill-Jer Wang, Feng-Cheng Hsu, Chao-Hsiang Yang, Shin-Puu Jeng, Cheng-Yi Hong, Chih-Hsien Lin, Dai-Jang Chen, Chen-Hua Lin
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Patent number: 11855059Abstract: Structures and methods of forming fan-out packages are provided. The packages described herein may include a cavity substrate, one or more semiconductor devices located in a cavity of the cavity substrate, and one or more redistribution structures. Embodiments include a cavity preformed in a cavity substrate. Various devices, such as integrated circuit dies, packages, or the like, may be placed in the cavity. Redistribution structures may also be formed.Type: GrantFiled: June 24, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hao Tsai, Techi Wong, Po-Yao Chuang, Shin-Puu Jeng, Meng-Wei Chou, Meng-Liang Lin
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Patent number: 11854955Abstract: A method includes forming an interposer, which includes forming a rigid dielectric layer, and removing portions of the rigid dielectric layer. The method further includes bonding a package component to an interconnect structure, and bonding the interposer to the interconnect structure. A spacer in the interposer has a bottom surface contacting a top surface of the package component, and the spacer includes a feature selected from the group consisting of a metal feature, the rigid dielectric layer, and combinations thereof. A die-saw is performed on the interconnect structure.Type: GrantFiled: July 23, 2021Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Po-Hao Tsai, Techi Wong, Meng-Wei Chou, Meng-Liang Lin, Po-Yao Chuang, Shin-Puu Jeng
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Patent number: 11855004Abstract: A package structure is provided. The package structure includes a first conductive pad in an insulating layer, a first under bump metallurgy structure under the first insulating layer, and a first conductive via in the insulating layer. The first conductive via is vertically connected to the first conductive pad and the first under bump metallurgy structure. In a plan view, a first area of the first under bump metallurgy structure is confined within a second area of the first conductive pad.Type: GrantFiled: June 17, 2021Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chia-Kuei Hsu, Ming-Chih Yew, Shu-Shen Yeh, Che-Chia Yang, Po-Yao Lin, Shin-Puu Jeng
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Patent number: 11855009Abstract: A chip package is provided. The chip package includes a substrate and a semiconductor chip over the substrate. The chip package also includes an upper plate extending across edges of the semiconductor chip. The chip package further includes a first support structure connecting a first corner portion of the substrate and a first corner of the upper plate. In addition, the chip package includes a second support structure connecting a second corner portion of the substrate and a second corner of the upper plate. The upper plate has a side edge connecting the first support structure and the second support structure, and the side edge extends across opposite edges of the semiconductor chip.Type: GrantFiled: July 1, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shu-Shen Yeh, Chin-Hua Wang, Kuang-Chun Lee, Po-Yao Lin, Shyue-Ter Leu, Shin-Puu Jeng
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Publication number: 20230411234Abstract: A device includes a package substrate, an interposer having a first side bonded to the package substrate, a first die bonded to a second side of the interposer, the second side being opposite the first side, a ring on the package substrate, wherein the ring surrounds the first die and the interposer; and a heat spreader over and coupled to the ring and the first die, wherein a first coefficient of thermal expansion of a first material of the ring and a second coefficient of thermal expansion of a second material of the heat spreader are different, and wherein in a cross-sectional view a combined structure of the heat spreader and the ring have a H-shaped profile.Type: ApplicationFiled: May 26, 2022Publication date: December 21, 2023Inventors: Shu-Shen Yeh, Yu Chen Lee, Po-Chen Lai, Po-Yao Lin, Shin-Puu Jeng, Yu-Sheng Lin, Chien-Hung Chen
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Publication number: 20230411345Abstract: A bonded assembly including a first structure and a second structure is provided. The first structure includes first metallic connection structures surrounded of which a passivation dielectric layer includes openings therein, and first metallic bump structures having a respective first horizontal bonding surface segment that is vertically recessed from a first horizontal plane including a distal horizontal surface of the passivation dielectric layer. The second structure includes second metallic bump structures having a respective second horizontal bonding surface segment that protrudes toward the first structure. The first metallic bump structures is bonded to the second metallic bump structures through solder material portions.Type: ApplicationFiled: June 10, 2022Publication date: December 21, 2023Inventors: Han-Hsiang Huang, Yen-Hao Chen, Chien-Sheng Chen, Shin-Puu Jeng
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Publication number: 20230411171Abstract: A method of forming a semiconductor structure includes the following operations. First deep vias are formed in a first glass layer. A first redistribution layer structure is formed on a first side of the first glass layer, and the first redistribution layer structure is electrically connected to the first deep vias. A carrier is bonded to the first redistribution layer structure. The first glass layer is grinded until surfaces of the first deep vias are exposed. A second redistribution layer structure is formed on a second side of the first glass layer opposite to the first side, and the second redistribution layer structure is electrically connected to the first deep vias.Type: ApplicationFiled: June 13, 2022Publication date: December 21, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jing-Ye Juang, Hsien-Wei Chen, Shin-Puu Jeng
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Patent number: 11848265Abstract: A semiconductor package is provided. The semiconductor package includes an encapsulating layer, a semiconductor die formed in the encapsulating layer, and an interposer structure covering the encapsulating layer. The interposer structure includes an insulating base having a first surface facing the encapsulating layer, and a second surface opposite the first surface. The interposer structure also includes insulting features formed on the first surface of the insulating base and extending into the encapsulating layer. The insulting features are arranged in a matrix and face a top surface of the semiconductor die. The interposer structure further includes first conductive features formed on the first surface of the insulating base and extending into the encapsulating layer. The first conductive features surround the matrix of the plurality of insulting features.Type: GrantFiled: August 12, 2021Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-Wen Wu, Techi Wong, Po-Hao Tsai, Po-Yao Chuang, Shih-Ting Hung, Shin-Puu Jeng
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Patent number: 11848305Abstract: An embodiment is a structure including a first semiconductor device and a second semiconductor device, a first set of conductive connectors mechanically and electrically bonding the first semiconductor device and the second semiconductor device, a first underfill between the first and second semiconductor devices and surrounding the first set of conductive connectors, a first encapsulant on at least sidewalls of the first and second semiconductor devices and the first underfill, and a second set of conductive connectors electrically coupled to the first semiconductor device, the second set of conductive connectors being on an opposite side of the first semiconductor device as the first set of conductive connectors.Type: GrantFiled: March 7, 2022Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shin-Puu Jeng, Po-Yao Chuang, Shuo-Mao Chen
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Publication number: 20230402339Abstract: In an embodiment, a method of forming a semiconductor device includes: attaching an integrated circuit die to an interposer; forming an encapsulant over the interposer and around the integrated circuit die, a top surface of the encapsulant and a top surface of the integrated circuit die being level; forming recesses in the encapsulant; and bonding the interposer to a package substrate, wherein after bonding the interposer to the package substrate, each of the recesses being along an outer edge of the encapsulant.Type: ApplicationFiled: June 14, 2022Publication date: December 14, 2023Inventors: Shu-Shen Yeh, Chin-Hua Wang, Chipta Priya Laksana, Po-Yao Lin, Shin-Puu Jeng