Abstract: A method is disclosed for designing a semiconductor circuit on a multi-project wafer (MPW). One or more standard modules designed by one or more vendors with verified functions are first identified. Some of the standard modules are charged based on usage. At least one reconfigurable module of the MPW is programmed by making one or more connections through one or more connection layers. The standard modules are further connected with the programmed reconfigurable module according to the predetermined design of the circuit. The completed circuit is then verified for final uses.

Abstract: A fuse resistance monitoring system is disclosed to comprise at least one non-regenerative sense amplifier; at least one fuse module having at least one fuse cell coupled to a first terminal of the sense amplifier; and a reference resistor coupled to a second terminal of the sense amplifier, wherein a source voltage node between the fuse module and the sense amplifier is monitored to reflect a resistance of the fuse cell.

Abstract: A method and system is disclosed for device trimming. A device trimming system comprises at least one reference device to be trimmed having a reference electrical parameter, at least one trimming device to be coupled with the reference device for forming a trimmed reference device providing an altered reference electrical parameter based on a combination of the reference device and the trimming device, and at least one electrical fuse based control module for controlling whether the trimming device is to be coupled with the reference device based on a state of the electrical fuse.

Abstract: A method and apparatus is disclosed for sharing multiple fuses with a programming device. A fuse circuit embodying features of the present invention comprises one or more one-time programmable electrical fuses coupled in parallel, a programming device coupled to the fuses, and a selection module coupled to the fuses for selecting a predetermined fuse, wherein upon a selection by the selection module, a programming voltage is imposed for inducing a programming current through the predetermined fuse.

Abstract: A configurable logic and memory block (CLMB) and a configurable logic device are disclosed. The CLMB includes one or more static random access memory (SRAM) cells, a first output module for generating a first output by reading at least one SRAM cell when the CLMB functions as an SRAM, a second output module for generating a second output by reading at least one SRAM cell when the CLMB functions as a program logic device (PLD), wherein data on one or more bitlines coupled to the SRAM cells are controllably feeding into the first and second output modules. The configurable logic device can provide various Boolean logic functions using pass gates.

Abstract: A smart memory computing system that uses smart memory for massive data storage as well as for massive parallel execution is disclosed. The data stored in the smart memory can be accessed just like the conventional main memory, but the smart memory also has many execution units to process data in situ. The smart memory computing system offers improved performance and reduced costs for those programs having massive data-level parallelism. This smart memory computing system is able to take advantage of data-level parallelism to improve execution speed by, for example, use of inventive aspects such as algorithm mapping, compiler techniques, architecture features, and specialized instruction sets.

Abstract: A thin-dielectric unit capacitor is disclosed having a first node coupled to a first circuit connection point and a second node coupled to a second circuit connection point. It further contains a first and second thin-dielectric capacitors connected in series between the first and second nodes, wherein a thickness of a gate dielectric for each thin-dielectric capacitor is less than 50 angstroms.

Abstract: A high voltage switch circuit is disclosed for reducing high voltage junction stresses. The circuit contains a cascode device structure having one or more transistors of a same type connected in a series and being operable with a normal operating voltage and a high operating voltage. The cascode device structure comprises a high operating voltage coupled to a first end of the device structure, a low voltage coupled to a second end, and one or more control voltages controllably coupled to the gates of the transistors, wherein at least one of the control voltages coupled to the gate of at least one transistor is raised to a medium voltage level that is higher than a normal operating voltage when operating under the high operating voltage for tolerating stress imposed thereon by the high operating voltage.

Abstract: The invention discloses a power up reset circuit. A power supply voltage follower connected to a power supply is used for proportionally following an increase of a supply voltage to output a power up reset signal. A pulse generation control circuit coupled to the power supply voltage follower is used for discharging the power supply voltage follower when the supply voltage exceeds a predefined threshold voltage, thereby causing the power up reset signal to produce a reset pulse.

Abstract: Innovative Innovative techniques over the conventional random number generators and randomization procedures are disclosed. The improved techniques use irrational numbers over the pseudo-random numbers generated by LFSR and use irrational number generators involve floating-point operations over the conventional integer arithmetic and logic operations. These innovative techniques can be applied to various cryptography applications such as hashes, ciphers, and random number generators. Particularly, the cubic root and inverse cubic root are two suitable functions for use in this invention.

Abstract: A method and apparatus for controlling compartmentalization of a cache memory. A cache memory including a plurality of storage components receives one or more externally generated cache compartment signals. Based on the one or more cache compartment signals, cache compartment logic in the cache memory selects one of the plurality of storage compartments to store data after a cache miss.

Abstract: A method and apparatus for controlling compartmentalization of a cache memory. A cache memory including a plurality of storage components receives one or more externally generated cache compartment signals. Based on the one or more cache compartment signals, cache compartment logic in the cache memory selects one of the plurality of storage compartments to store data after a cache miss.

Abstract: A technique for concurrently detecting a repetitive occurrence of a bit pattern in a bit string. Successive bits of the bit string are separated into bit groupings and the combined bits are analyzed for the presence of the bit pattern. The logic for subsequent analysis to reduce the number of groupings is achieved by the use of a hierarchically decreasing logic array. At each level of the hierarchy, the bit analysis is reduced until a final output is reached. This final output provides state and address outputs for identifying the detection of the bit pattern occurrences and the address where the bit patterns occur.

Abstract: A microprocessor includes an instruction cache and a branch target buffer to implement a branch prediction scheme. The instruction cache, which stores branch instructions, is organized into cache lines and sets to implement set associative caching with memory that stores instructions. The branch target buffer includes storage locations organized into lines such that instructions stored in a cache line of the instruction cache correspond to a line in the branch target buffer. The storage locations permit storage of a branch target address that corresponds to any one of the sets in the cache line of the instruction cache to permit storage of branch information for multiple branch instructions when a cache line of a set stores more than one branch instruction. Thus, the resources of the branch target buffer are shared among the sets of the instruction cache.

Abstract: An improved memory type multi-ported data storage device is disclosed. The storage device operates to overcome the cell stability problems associated with the prior art by unidirectionally isolating memory cells of the multi-ported data storage device from read ports of the multi-ported data storage device. The unidirectional isolation operates to prevent external signals from the read ports and read port loading from influencing data stored in the memory cells, but continues to allow the memory cells to be read by the read ports associated therewith. The improved multi-ported data storage device not only allows simultaneous access to its memory cells by a large number of read ports without fear that cell stability will cause corruption of the memory cells, but also requires only a minimal amount of additional die area. Moreover, access time is independent of the number of ports being simultaneously accessed.

Abstract: A method and processor design for detecting a specified bit pattern based on the contents of one or more registers, each register having a plurality of bits. The invention is well suited for parallel processing. The method begins by combining successive sets of contiguous bits to generate a state value and output value representative of the values in each set of contiguous bits. The state values and output values so generated become the values for level 1 of a hierarchy of state and output values. The manner in which the states are assigned and the number of states will, in general, depend on the specific bit pattern being sought. At each successive level in the hierarchy, sets of continuous output values and state values from the previous level are combined to generate the output values and state values for the level in question. The number of output and state values is reduced by at least a factor of two at each level of the hierarchy.