Abstract: This invention discloses a dynamic random access memory (DRAM) device comprising a first bit-line coupled to a first terminal of at least one memory cell capacitor through one or more pass transistors, a second bit-line coupled to a first terminal of at least one reference cell capacitor through one or more pass transistors, and a cell plate connected to both a second terminal of at least one memory cell capacitor and a second terminal of at least one reference cell capacitor, wherein the cell plate is biased at approximately one half of a voltage difference between a positive supply voltage (Vdd) and a complementary lower supply voltage (Vss), and wherein the reference cell capacitor does not store any charge prior to a reading operation, and wherein both the first and second bit-lines are pre-charged to either Vdd or Vss prior to the reading operation.

Abstract: This invention discloses a dynamic random access memory (DRAM) device comprising a first bit-line coupled to a first terminal of at least one memory cell capacitor through one or more pass transistors, a second bit-line coupled to a first terminal of at least one reference cell capacitor through one or more pass transistors, and a cell plate connected to both a second terminal of at least one memory cell capacitor and a second terminal of at least one reference cell capacitor, wherein the cell plate is biased at approximately one half of a voltage difference between a positive supply voltage (Vdd) and a complementary lower supply voltage (Vss), and wherein the reference cell capacitor does not store any charge prior to a reading operation, and wherein both the first and second bit-lines are pre-charged to either Vdd or Vss prior to the reading operation.

Abstract: A split gate memory cell. First and second well regions of respectively first and second conductivity types are formed in the substrate. A floating gate is disposed on a junction of the first and second well regions and insulated from the substrate. A control gate is disposed over the sidewall of the floating gate and insulated from the substrate and the floating gate and partially extends to the upper surface of the floating gate. A doping region of the first conductivity type is formed in the second well region. The first well region and the doping region respectively serve as source and drain regions of the split gate memory cell.

Abstract: A waveguide in semiconductor integrated circuit is disclosed, the waveguide comprises a horizontal first metal plate, a horizontal second metal plate above the first metal plate, separated by an insulation material, and a plurality of metal vias positioned in two parallel lines, running vertically through the insulation material in contacts with both the first and second metal plates, wherein the first and second metal plates and the plurality of metal vias form a metal enclosure in a cross-sectional view that can serve as a waveguide.

Abstract: A method for testing a memory with cell plates and bit-line plates comprises putting the memory in a test mode, applying a test pattern to the memory, then providing a first voltage higher than Vdd/2 to the cell plate when writing a ‘1’ to a predetermined cell, providing a second voltage lower than Vdd/2 to the cell plate when writing a ‘0’ to a predetermined cell, wherein the first and second voltages are applied to emulate weak charge storage in the memory cell, similarly, providing a third voltage higher than Vdd/2 to the bit-line plate when expecting to read a ‘1’ from a predetermined cell, and providing a fourth voltage lower than Vdd/2 to the bit-line plate when expecting to read a ‘0’ from a predetermined cell, wherein the third and fourth voltages are applied to emulate charge decay in the memory cell.

Abstract: The present invention discloses a semiconductor memory having an array of storage cells with at least one PMOS transistor, the semiconductor memory comprising at least one mode bit for representing data stored in the array of storage cells are either true or inverted, a plurality of read-toggle drivers coupled on a plurality of data output paths for inverting the data outputs only when the mode bit indicates that the array of storage cells are storing inverted data, and a plurality of write-toggle drivers coupled on a plurality of data input paths for inverting the data inputs only when the mode bit indicates that the array of storage cells are storing inverted data and for writing back inverted data into the array of storage cells during a refreshing cycle.

Abstract: A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or more active regions, wherein the extended active region has at least a length twice as much as a distance between gates of two neighboring operational devices.

Abstract: A method and system is disclosed for protecting electrical fuse circuitry. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.

Abstract: A method and system is disclosed for protecting electrical fuse circuitries. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.

Abstract: A method and system is disclosed for conducting built-in-self-test (BIST) in a circuit under test. After allocating at least one memory segment with a predetermined size in at least one memory module as a test result module, the built-in-self-test is conducted for the circuit under test without testing the test result module. The test results are stored in the test result module.

Abstract: A micro-motor memory device includes at least one rotor having at least one indicator for rotating about an axis; and at least one stator placed adjacent to the rotor for electromagnetically or physically engaging the rotor to rotate the indicator to at least one predetermined angular position for representing stored data. The rotor and the stator are constructed on a semiconductor substrate by using micro-electro-mechanic-system technology.

Abstract: A circuit and method are disclosed for reducing device mismatch due to trench isolation related stress. One or more extended active regions are formed on the substrate, wherein the active regions being extended from one or more ends thereof, and one or more operational devices are placed on one or more active regions, wherein the extended active region has at least a length twice as much as a distance between gates of two neighboring operational devices.

Abstract: A high voltage switch circuit is disclosed for reducing high voltage junction stresses. The circuit contains a cascode device structure having one or more transistors of a same type connected in a series and being operable with a normal operating voltage and a high operating voltage. The cascode device structure comprises a high operating voltage coupled to a first end of the device structure, a low voltage coupled to a second end, and one or more control voltages controllably coupled to the gates of the transistors, wherein at least one of the control voltages coupled to the gate of at least one transistor is raised to a medium voltage level that is higher than a normal operating voltage when operating under the high operating voltage for tolerating stress imposed thereon by the high operating voltage.

Abstract: A method is disclosed for utilizing mixed low threshold voltage (low-Vt) and high threshold voltage (high-Vt) devices in a cell-based design such that a tradeoff of both the circuit speed and power performance may be achieved. Using cells having non-uniform threshold devices for designing circuit, the speed or/and power optimization is comparable to fully custom designs.

Abstract: The present invention discloses a bipolar device. An emitter is formed in a semiconductor substrate. A collector is laterally spaced from the emitter in the substrate. A gate terminal is formed on the substrate, defining a space between the emitter and the collector. An extrinsic base is formed on the substrate with a predetermined distance from either the emitter or the collector, wherein the base, the emitter, the collector and the gate terminal are located in an active area defined by a hole in a surrounding isolation structure in the substrate.

Abstract: The present disclosure provides an electrical fuse cell with redundancy features and the method for operating the same. The fuse cell includes a first set of electrical fuses having at least one electrical fuse contained therein, and a second set of electrical fuses having at least one electrical fuse for providing redundancy to at least one fuse of the first set, wherein if one of the first set of electrical fuses is defective, at least one of the second set of the electrical fuses can be programmed to provide a redundancy function of the defective fuse.

Abstract: A method and system is disclosed for protecting electrical fuse circuitries. A electrical fuse circuit with electrostatic discharge (ESD) protection has at least one electrical fuse, a programming device coupled in series with the electrical fuse having at least a transistor for receiving a control signal for controlling a programming current flowing through the electrical fuse, a voltage source coupled to the fuse and the programming device for providing the programming current, and a protection module coupled to a gate of the transistor at its first end for reducing charges accumulated at the gate of the transistor due to electric static charges arriving at the voltage source, thereby preventing the programming device from accidentally programming the fuse.

Abstract: The present invention provides improve device designs for high voltage tolerance and methods for making the same. In one embodiment, a low doped drain extension (LDD) region is extended to sustain higher voltages with minimal extra space and processing. In another example, a trench isolation barrier is placed between the gate and an active region in a well. In another example, an additional trench isolation barrier is placed under the middle of the gate. The trench is filled with dielectric such as oxides, with a small upper portion replaced with recrystallized silicon. These disclosed transistor devices can have parameters controlled so that predetermined performances of the transistor devices can be achieved.

Abstract: An electrical fuse is disclosed. It is formed by a silicide layer on a polysilicon layer, with a first dielectric section separating the electrical fuse from a semiconductor substrate and a second dielectric section separating the electrical fuse from at least one electrical conductor directly above the fuse. The polysilicon layer is at least 2000 Angstroms in thickness and no more than 0.14 um in width and the second dielectric section contains substantially low-K materials.

Abstract: Fuse circuit designs and the use thereof are disclosed. In one example, a fuse circuit providing predictable total resistances for multiple rounds of programming comprises a predetermined number of fuse stages coupled in series. Each stage comprises a first and a second connecting nodes, a fuse connected between the first and second connecting nodes, a first resistor with its first end connected to the first connecting node, and a second resistor with its first end connected to the second connecting node, wherein the first and second resistors connect to a third and a fourth connecting nodes, which are the first and second connecting nodes of a next fuse stage respectively, through their second ends.