Patents by Inventor Shing-Chao Chen

Shing-Chao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230360949
    Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film. The redistribution structure is electrically connected to the conductive bumps.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
  • Patent number: 11776838
    Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided.
    Type: Grant
    Filed: November 15, 2021
    Date of Patent: October 3, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
  • Publication number: 20220336363
    Abstract: A package structure is provided. The package structure includes a semiconductor chip and a first dielectric layer over the semiconductor chip and extending across opposite sidewalls of the semiconductor chip. The package structure also includes a conductive layer over the first dielectric layer, and the conductive layer has multiple first protruding portions extending into the first dielectric layer. The package structure further includes a second dielectric layer over the first dielectric layer and the conductive layer. The second dielectric layer has multiple second protruding portions extending into the first dielectric layer. Each of the first protruding portions and the second protruding portions is thinner than the first dielectric layer.
    Type: Application
    Filed: July 1, 2022
    Publication date: October 20, 2022
    Inventors: Shing-Chao CHEN, Chih-Wei LIN, Tsung-Hsien CHIANG, Ming-Da CHENG, Ching-Hua HSIEH
  • Patent number: 11404381
    Abstract: A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a first dielectric layer over the semiconductor die and the protection layer. The first dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the first dielectric layer. In addition, the chip package includes a second dielectric layer over the conductive layer and filling some of the cutting scratches. Bottoms of the cutting scratches are positioned at height levels that are lower than a topmost surface of the first dielectric layer and higher than a topmost surface of the semiconductor die.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: August 2, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Tsung-Hsien Chiang, Ming-Da Cheng, Ching-Hua Hsieh
  • Publication number: 20220076982
    Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided.
    Type: Application
    Filed: November 15, 2021
    Publication date: March 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
  • Publication number: 20210366885
    Abstract: A package includes a first die, a second die, a bridge structure, a first redistribution structure, and an encapsulant. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die. The bridge structure includes a plurality of routing patterns and a plurality of connectors disposed on the plurality of routing patterns. The first redistribution structure is sandwiched between the first die and the bridge structure and is sandwiched between the second die and the bridge structure. The plurality of connectors of the bridge structure is in physical contact with the first redistribution structure. The encapsulant encapsulates the bridge structure. The plurality of routing patterns and the plurality of connectors of the bridge structure are completely spaced apart from the encapsulant.
    Type: Application
    Filed: August 9, 2021
    Publication date: November 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
  • Patent number: 11177156
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
  • Publication number: 20210280520
    Abstract: A method for forming a chip package is provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes planarizing a first portion of the dielectric layer and planarizing a second portion of the dielectric layer after the first portion of the dielectric layer is planarized. In addition, the method includes forming a conductive layer over the dielectric layer after the first portion and the second portion of the dielectric layer are planarized.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: Shing-Chao CHEN, Chih-Wei LIN, Tsung-Hsien CHIANG, Ming-Da CHENG, Ching-Hua HSIEH
  • Patent number: 11088124
    Abstract: A package includes a first redistribution structure, a bridge structure, an adhesive layer, a plurality of conductive pillars, an encapsulant, a first die, and a second die. The bridge structure is disposed on the first redistribution structure. The adhesive layer is disposed between the bridge structure and the first redistribution structure. The conductive pillars surround the bridge structure. A height of the conductive pillars is substantially equal to a sum of a height of the adhesive layer and a height of the bridge structure. The encapsulant encapsulates the bridge structure, the adhesive layer, and the conductive pillars. The first die and the second die are disposed over the bridge structure. The first die is electrically connected to the second die through the bridge structure. The first die and the second die are electrically connected to the first redistribution structure through the conductive pillars.
    Type: Grant
    Filed: August 14, 2018
    Date of Patent: August 10, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
  • Patent number: 10964663
    Abstract: A method includes bringing into contact respective first sides of a plurality of dies and a die attach film on a major surface of a carrier wafer, and simultaneously heating portions of the die attach film contacting the plurality of dies in order to simultaneously bond the plurality of dies to the die attach film.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shing-Chao Chen, Chung-Shi Liu, Ming-Da Cheng
  • Patent number: 10950572
    Abstract: A method includes bringing into contact respective first sides of a plurality of dies and a die attach film on a major surface of a carrier wafer, and simultaneously heating portions of the die attach film contacting the plurality of dies in order to simultaneously bond the plurality of dies to the die attach film.
    Type: Grant
    Filed: October 31, 2019
    Date of Patent: March 16, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Shing-Chao Chen, Chung-Shi Liu, Ming-Da Cheng
  • Publication number: 20210057259
    Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices.
    Type: Application
    Filed: August 22, 2019
    Publication date: February 25, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
  • Patent number: 10867953
    Abstract: A manufacturing method of integrated fan-out package includes following steps. First and second dies are provided on adhesive layer formed on carrier. Heights of first and second dies are different. First and second dies respectively has first and second conductive posts each having substantially a same height. The dies are pressed against adhesive layer to make active surfaces thereof be in direct contact with adhesive layer and conductive posts thereof be submerged into adhesive layer. Adhesive layer is cured. Encapsulant is formed to encapsulate the dies. Carrier is removed from adhesive layer. Heights of first and second conductive posts are reduced and portions of the adhesive layer is removed. First and second conductive posts are laterally wrapped by and exposed from adhesive layer. Top surfaces of first and second conductive posts are leveled. Redistribution structure is formed over adhesive layer and is electrically connected to first and second conductive posts.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 15, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ai-Tee Ang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Ching-Yao Lin
  • Patent number: 10840111
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a protection layer encapsulating the semiconductor die. The chip package also includes a conductive structure in the protection layer and separated from the semiconductor die by the protection layer. The chip package further includes an interconnection structure over the conductive structure and the protection layer. The interconnection structure has a protruding portion between the conductive structure and the semiconductor die, and the protruding portion extends into the protection layer.
    Type: Grant
    Filed: April 13, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Meng-Tse Chen, Hui-Min Huang, Ming-Da Cheng, Kuo-Lung Pan, Wei-Sen Chang, Tin-Hao Kuo, Hao-Yi Tsai
  • Patent number: 10797038
    Abstract: An embodiment is a method including bonding a first package to a first set of conductive pads of a second package with a first set of solder joints, testing the first package for defects, heating the first set of solder joints by directing a laser beam at a surface of the first package based on testing the first package for defects, after the first set of solder joints are heated, removing the first package, and bonding a third package to the first set of conductive pads of the second package.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: October 6, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, An-Jhih Su, Shing-Chao Chen, Ching-Hua Hsieh, Chung-Shi Liu, Der-Chyang Yeh, Ming-Da Cheng
  • Publication number: 20200135652
    Abstract: A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a first dielectric layer over the semiconductor die and the protection layer. The first dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the first dielectric layer. In addition, the chip package includes a second dielectric layer over the conductive layer and filling some of the cutting scratches. Bottoms of the cutting scratches are positioned at height levels that are lower than a topmost surface of the first dielectric layer and higher than a topmost surface of the semiconductor die.
    Type: Application
    Filed: December 23, 2019
    Publication date: April 30, 2020
    Inventors: Shing-Chao CHEN, Chih-Wei LIN, Tsung-Hsien CHIANG, Ming-Da CHENG, Ching-Hua HSIEH
  • Publication number: 20200066673
    Abstract: A method includes bringing into contact respective first sides of a plurality of dies and a die attach film on a major surface of a carrier wafer, and simultaneously heating portions of the die attach film contacting the plurality of dies in order to simultaneously bond the plurality of dies to the die attach film.
    Type: Application
    Filed: October 31, 2019
    Publication date: February 27, 2020
    Inventors: Chen-Hua Yu, Shing-Chao Chen, Chung-Shi Liu, Ming-Da Cheng
  • Publication number: 20200066674
    Abstract: A method includes bringing into contact respective first sides of a plurality of dies and a die attach film on a major surface of a carrier wafer, and simultaneously heating portions of the die attach film contacting the plurality of dies in order to simultaneously bond the plurality of dies to the die attach film.
    Type: Application
    Filed: November 1, 2019
    Publication date: February 27, 2020
    Inventors: Chen-Hua Yu, Shing-Chao Chen, Chung-Shi Liu, Ming-Da Cheng
  • Publication number: 20200058627
    Abstract: A package includes a first redistribution structure, a bridge structure, an adhesive layer, a plurality of conductive pillars, an encapsulant, a first die, and a second die. The bridge structure is disposed on the first redistribution structure. The adhesive layer is disposed between the bridge structure and the first redistribution structure. The conductive pillars surround the bridge structure. A height of the conductive pillars is substantially equal to a sum of a height of the adhesive layer and a height of the bridge structure. The encapsulant encapsulates the bridge structure, the adhesive layer, and the conductive pillars. The first die and the second die are disposed over the bridge structure. The first die is electrically connected to the second die through the bridge structure. The first die and the second die are electrically connected to the first redistribution structure through the conductive pillars.
    Type: Application
    Filed: August 14, 2018
    Publication date: February 20, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
  • Patent number: 10515900
    Abstract: A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a dielectric layer over the semiconductor die and the protection layer. The dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the dielectric layer and filling some of the cutting scratches.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: December 24, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD
    Inventors: Shing-Chao Chen, Chih-Wei Lin, Tsung-Hsien Chiang, Ming-Da Cheng, Ching-Hua Hsieh