Patents by Inventor Shing-Chao Chen
Shing-Chao Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250349808Abstract: A package includes a first redistribution structure, a first die, a second die, a bridge structure, and an encapsulant. The first redistribution structure has a first side and a second side opposite to the first side. The first die and the second die are disposed on the first side of the first redistribution structure. The bridge structure is disposed on the second side of the first redistribution structure. The bridge structure includes routing patterns and connectors disposed on the routing patterns. A lateral dimension of the bridge structure is smaller than a lateral dimension of the first redistribution structure. The encapsulant is disposed on the second side of the first redistribution structure. The routing patterns and the connectors of the bridge structure are completely spaced apart from the encapsulant. The encapsulant is in physical contact with sidewalls of the bridge structure.Type: ApplicationFiled: July 23, 2025Publication date: November 13, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
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Patent number: 12444719Abstract: A package includes a redistribution structure, a bridge die, conductive pillars, connectors, a first die, first solder joints, and second solder joints. The bridge die includes a substrate, a dielectric layer disposed on the substrate, and routing patterns embedded in the dielectric layer. The conductive pillars are coupled to the redistribution structure at a position that is laterally offset from the bridge die. The connectors are coupled to the bridge die and the redistribution structure, such that the bridge die is electrically coupled to the redistribution structure through at least the connectors. The first solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the bridge die. The second solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the conductive pillars.Type: GrantFiled: June 6, 2024Date of Patent: October 14, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
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Publication number: 20250285905Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film. The redistribution structure is electrically connected to the conductive bumps.Type: ApplicationFiled: May 21, 2025Publication date: September 11, 2025Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
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Patent number: 12322640Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film. The redistribution structure is electrically connected to the conductive bumps.Type: GrantFiled: July 20, 2023Date of Patent: June 3, 2025Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
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Patent number: 12125797Abstract: A package structure is provided. The package structure includes a semiconductor chip and a first dielectric layer over the semiconductor chip and extending across opposite sidewalls of the semiconductor chip. The package structure also includes a conductive layer over the first dielectric layer, and the conductive layer has multiple first protruding portions extending into the first dielectric layer. The package structure further includes a second dielectric layer over the first dielectric layer and the conductive layer. The second dielectric layer has multiple second protruding portions extending into the first dielectric layer. Each of the first protruding portions and the second protruding portions is thinner than the first dielectric layer.Type: GrantFiled: July 1, 2022Date of Patent: October 22, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shing-Chao Chen, Chih-Wei Lin, Tsung-Hsien Chiang, Ming-Da Cheng, Ching-Hua Hsieh
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Publication number: 20240321848Abstract: A package includes a redistribution structure, a bridge die, conductive pillars, connectors, a first die, first solder joints, and second solder joints. The bridge die includes a substrate, a dielectric layer disposed on the substrate, and routing patterns embedded in the dielectric layer. The conductive pillars are coupled to the redistribution structure at a position that is laterally offset from the bridge die. The connectors are coupled to the bridge die and the redistribution structure, such that the bridge die is electrically coupled to the redistribution structure through at least the connectors. The first solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the bridge die. The second solder joints are coupled to the redistribution structure and the first die, such that the first die is electrically coupled to the conductive pillars.Type: ApplicationFiled: June 6, 2024Publication date: September 26, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
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Patent number: 12080653Abstract: A method for forming a chip package is provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes planarizing a first portion of the dielectric layer and planarizing a second portion of the dielectric layer after the first portion of the dielectric layer is planarized. In addition, the method includes forming a conductive layer over the dielectric layer after the first portion and the second portion of the dielectric layer are planarized.Type: GrantFiled: May 24, 2021Date of Patent: September 3, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shing-Chao Chen, Chih-Wei Lin, Tsung-Hsien Chiang, Ming-Da Cheng, Ching-Hua Hsieh
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Patent number: 12033992Abstract: A package includes a first die, a second die, a bridge structure, a first redistribution structure, and an encapsulant. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die. The bridge structure includes a plurality of routing patterns and a plurality of connectors disposed on the plurality of routing patterns. The first redistribution structure is sandwiched between the first die and the bridge structure and is sandwiched between the second die and the bridge structure. The plurality of connectors of the bridge structure is in physical contact with the first redistribution structure. The encapsulant encapsulates the bridge structure. The plurality of routing patterns and the plurality of connectors of the bridge structure are completely spaced apart from the encapsulant.Type: GrantFiled: August 9, 2021Date of Patent: July 9, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
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Publication number: 20230360949Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film. The redistribution structure is electrically connected to the conductive bumps.Type: ApplicationFiled: July 20, 2023Publication date: November 9, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
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Patent number: 11776838Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided.Type: GrantFiled: November 15, 2021Date of Patent: October 3, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
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Publication number: 20220336363Abstract: A package structure is provided. The package structure includes a semiconductor chip and a first dielectric layer over the semiconductor chip and extending across opposite sidewalls of the semiconductor chip. The package structure also includes a conductive layer over the first dielectric layer, and the conductive layer has multiple first protruding portions extending into the first dielectric layer. The package structure further includes a second dielectric layer over the first dielectric layer and the conductive layer. The second dielectric layer has multiple second protruding portions extending into the first dielectric layer. Each of the first protruding portions and the second protruding portions is thinner than the first dielectric layer.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: Shing-Chao CHEN, Chih-Wei LIN, Tsung-Hsien CHIANG, Ming-Da CHENG, Ching-Hua HSIEH
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Patent number: 11404381Abstract: A chip package is provided. The chip package includes a semiconductor die and a protection layer surrounding the semiconductor die. The chip package also includes a first dielectric layer over the semiconductor die and the protection layer. The first dielectric layer has an upper surface with cutting scratches. The chip package further includes a conductive layer over the first dielectric layer. In addition, the chip package includes a second dielectric layer over the conductive layer and filling some of the cutting scratches. Bottoms of the cutting scratches are positioned at height levels that are lower than a topmost surface of the first dielectric layer and higher than a topmost surface of the semiconductor die.Type: GrantFiled: December 23, 2019Date of Patent: August 2, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTDInventors: Shing-Chao Chen, Chih-Wei Lin, Tsung-Hsien Chiang, Ming-Da Cheng, Ching-Hua Hsieh
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Publication number: 20220076982Abstract: A semiconductor package includes a semiconductor device, an encapsulating material encapsulating the semiconductor device, and a redistribution structure disposed over the encapsulating material and the semiconductor device. The semiconductor device includes an active surface having conductive bumps and a dielectric film encapsulating the conductive bumps, where a material of the dielectric film comprises an epoxy resin and a filler. The conductive bumps are isolated from the encapsulating material by the dielectric film, and the redistribution structure is electrically connected to the conductive bumps. A manufacturing method of a semiconductor package is also provided.Type: ApplicationFiled: November 15, 2021Publication date: March 10, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
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Publication number: 20210366885Abstract: A package includes a first die, a second die, a bridge structure, a first redistribution structure, and an encapsulant. The first die and the second die are disposed side by side. The bridge structure is disposed over the first die and the second die. The bridge structure includes a plurality of routing patterns and a plurality of connectors disposed on the plurality of routing patterns. The first redistribution structure is sandwiched between the first die and the bridge structure and is sandwiched between the second die and the bridge structure. The plurality of connectors of the bridge structure is in physical contact with the first redistribution structure. The encapsulant encapsulates the bridge structure. The plurality of routing patterns and the plurality of connectors of the bridge structure are completely spaced apart from the encapsulant.Type: ApplicationFiled: August 9, 2021Publication date: November 25, 2021Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
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Patent number: 11177156Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices.Type: GrantFiled: August 22, 2019Date of Patent: November 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin
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Publication number: 20210280520Abstract: A method for forming a chip package is provided. The method includes disposing a semiconductor die over a carrier substrate and forming a protection layer over the carrier substrate to surround the semiconductor die. The method also includes forming a dielectric layer over the protection layer and the semiconductor die. The method further includes planarizing a first portion of the dielectric layer and planarizing a second portion of the dielectric layer after the first portion of the dielectric layer is planarized. In addition, the method includes forming a conductive layer over the dielectric layer after the first portion and the second portion of the dielectric layer are planarized.Type: ApplicationFiled: May 24, 2021Publication date: September 9, 2021Inventors: Shing-Chao CHEN, Chih-Wei LIN, Tsung-Hsien CHIANG, Ming-Da CHENG, Ching-Hua HSIEH
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Patent number: 11088124Abstract: A package includes a first redistribution structure, a bridge structure, an adhesive layer, a plurality of conductive pillars, an encapsulant, a first die, and a second die. The bridge structure is disposed on the first redistribution structure. The adhesive layer is disposed between the bridge structure and the first redistribution structure. The conductive pillars surround the bridge structure. A height of the conductive pillars is substantially equal to a sum of a height of the adhesive layer and a height of the bridge structure. The encapsulant encapsulates the bridge structure, the adhesive layer, and the conductive pillars. The first die and the second die are disposed over the bridge structure. The first die is electrically connected to the second die through the bridge structure. The first die and the second die are electrically connected to the first redistribution structure through the conductive pillars.Type: GrantFiled: August 14, 2018Date of Patent: August 10, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin, Sheng-Chieh Yang
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Patent number: 10964663Abstract: A method includes bringing into contact respective first sides of a plurality of dies and a die attach film on a major surface of a carrier wafer, and simultaneously heating portions of the die attach film contacting the plurality of dies in order to simultaneously bond the plurality of dies to the die attach film.Type: GrantFiled: November 1, 2019Date of Patent: March 30, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Shing-Chao Chen, Chung-Shi Liu, Ming-Da Cheng
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Patent number: 10950572Abstract: A method includes bringing into contact respective first sides of a plurality of dies and a die attach film on a major surface of a carrier wafer, and simultaneously heating portions of the die attach film contacting the plurality of dies in order to simultaneously bond the plurality of dies to the die attach film.Type: GrantFiled: October 31, 2019Date of Patent: March 16, 2021Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Shing-Chao Chen, Chung-Shi Liu, Ming-Da Cheng
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Publication number: 20210057259Abstract: A manufacturing method of a semiconductor device includes the following steps. A semiconductor wafer having an active side and a back side opposite to the active side is provided. A plurality of conductive bumps are provided on the active side. A protection film is laminated on the active side, wherein the protection film includes a dielectric film covering the plurality of conductive bumps and a cover film covering the dielectric film. A thinning process is performed on the back side to form a thinned semiconductor wafer. The cover film is removed from the dielectric film. A singularization process is performed on the thinned semiconductor wafer with the dielectric film to form a plurality of semiconductor devices.Type: ApplicationFiled: August 22, 2019Publication date: February 25, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Chieh Yang, Shing-Chao Chen, Ching-Hua Hsieh, Chih-Wei Lin