Abstract: Devices and processes for preparing devices are described for reducing resonance of spurious waves in a bulk acoustic resonator. A first electrode is coupled to a first side of a piezoelectric layer and a second electrode is coupled to a second side of the piezoelectric layer. The piezoelectric layer is configured to resonate in response to an electrical signal applied between the first electrode and the second electrode. Perforations in the first electrode, the piezoelectric layer and/or the second electrode, and/or posts or beams supporting the second electrode, reduce resonance of spurious waves.

Abstract: Devices and processes for preparing devices are described for a bulk acoustic wave resonator. A stack includes a first electrode that is coupled to a first side of a piezoelectric layer and a second electrode that is coupled to a second side of the piezoelectric layer. The stack is configured to resonate in response to an electrical signal applied between the first electrode and the second electrode. A cavity frame is coupled to the first electrode and to the substrate. The cavity frame forms a perimeter around a cavity. Optionally, a heat dissipating frame is formed and coupled to the second electrode. The cavity frame and/or the heat dissipating frame improve the thermal stability of the bulk acoustic resonator.

Abstract: Devices and processes for preparing devices are described for reducing resonance of spurious waves in a bulk acoustic resonator. A first electrode is coupled to a first side of a piezoelectric layer and a second electrode is coupled to a second side of the piezoelectric layer. The piezoelectric layer is configured to resonate in response to an electrical signal applied between the first electrode and the second electrode. Perforations in the first electrode, the piezoelectric layer and/or the second electrode, and/or posts or beams supporting the second electrode, reduce resonance of spurious waves.

Abstract: A device includes a semiconductor die. The semiconductor die includes a plurality of semiconductor layers disposed on a GaAs substrate, including a first semiconductor layer having a first band-gap and a second semiconductor layer having a second band-gap. The semiconductor die further includes a contact layer disposed epitaxially upon the first semiconductor layer. The contact layer has a thickness that is less than a critical thickness. The second semiconductor layer is epitaxially disposed upon the contact layer. The contact layer has a third band-gap that is less than the first band-gap and the second band-gap. The semiconductor die further includes a conductive layer disposed upon the contact layer to form an ohmic contact. The conductive layer comprises one or more metal layers compatible with silicon processing techniques.

Abstract: A device includes a semiconductor die. The semiconductor die includes a plurality of semiconductor layers disposed on a GaAs substrate, including a first semiconductor layer having a first band-gap and a second semiconductor layer having a second band-gap. The semiconductor die further includes a contact layer disposed epitaxially upon the first semiconductor layer. The contact layer has a thickness that is less than a critical thickness. The second semiconductor layer is epitaxially disposed upon the contact layer. The contact layer has a third band-gap that is less than the first band-gap and the second band-gap. The semiconductor die further includes a conductive layer disposed upon the contact layer to form an ohmic contact. The conductive layer comprises one or more metal layers compatible with silicon processing techniques.

Abstract: A semiconductor device having a tunable capacitance is disclosed, comprising a substrate, a semiconductor base layer comprising a first semiconductor material having a first band-gap, and a plurality of successive semiconductor layers positioned between the substrate and the semiconductor base layer. The plurality of successive semiconductor layers includes a tuning layer comprising a second semiconductor material having a second band-gap larger than the first band-gap. Furthermore, the tuning layer has a non-uniform doping profile with doping concentration that varies in accordance with distance from a surface of the tuning layer proximal to the semiconductor base layer. The tunable capacitance of the semiconductor device varies in accordance with an applied voltage between the base layer and one of the successive semiconductor layers.

Abstract: A semiconductor device having a tunable capacitance is disclosed, comprising a substrate, a semiconductor base layer comprising a first semiconductor material having a first band-gap, and a plurality of successive semiconductor layers positioned between the substrate and the semiconductor base layer. The plurality of successive semiconductor layers includes a tuning layer comprising a second semiconductor material having a second band-gap larger than the first band-gap. Furthermore, the tuning layer has a non-uniform doping profile with doping concentration that varies in accordance with distance from a surface of the tuning layer proximal to the semiconductor base layer. The tunable capacitance of the semiconductor device varies in accordance with an applied voltage between the base layer and one of the successive semiconductor layers.