Abstract: A chip package structure includes at least one chip, at least one thermally conductive element, a molding compound, and a redistribution layer. The respective chip has an active surface and a back surface opposite to each other and a plurality of electrodes disposed on the active surface. The thermally conductive element is disposed on the back surface of the respective chip. The molding compound encapsulates the chip and the thermally conductive element and has an upper surface and a lower surface opposite to each other. A bottom surface of each of the electrodes of the respective chip is aligned with the lower surface of the molding compound. The molding compound exposes a top surface of the respective thermally conductive element. The redistribution layer is disposed on the lower surface of the molding compound and electrically connected to the electrodes of the respective chip.

Abstract: A package structure is disclosed herein. The package structure includes an insulating composite layer, a sealant disposed on the insulating composite layer, a first chip embedded in the sealant and having a plurality of first conductive pads exposed through the sealant, a circuit layer module having a plurality of circuit layers and a plurality of dielectric layers having a plurality of conductive vias, a second chip embedded in the circuit layer module and has a plurality of second conductive pads electrically connected to the circuit layers through the conductive vias, and a protecting layer having a plurality of openings disposed on the circuit layer module, in which the openings expose a portion of the circuit layer module.

Abstract: A method of feeding underfill material to fill a space between a semiconductor die and a substrate onto which the semiconductor die has been bonded, the method comprises positioning a stencil over the semiconductor die. The stencil has an elongated slot extending adjacent to an edge of the semiconductor die. Underfill material is printed through the slot such that the underfill material falls through the slot onto the substrate next to the edge of the semiconductor die. Thereafter, the underfill material is heated such that the underfill material flows across the space between the semiconductor die and the substrate from the edge of the semiconductor die to an opposite edge thereof through capillary action.

Abstract: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.

Abstract: A method of feeding underfill material to fill a space between a semiconductor die and a substrate onto which the semiconductor die has been bonded, the method comprises positioning a stencil over the semiconductor die. The stencil has an elongated slot extending adjacent to an edge of the semiconductor die. Underfill material is printed through the slot such that the underfill material falls through the slot onto the substrate next to the edge of the semiconductor die. Thereafter, the underfill material is heated such that the underfill material flows across the space between the semiconductor die and the substrate from the edge of the semiconductor die to an opposite edge thereof through capillary action.

Abstract: The present invention is concerned with a staining dye for staining a biological cell, comprising dye molecules with a positively charged polar head group for attraction to cell membrane of the cell and for refraining the dye molecules from entering the cytoplasm, and one or more hydrophobic groups for interaction with phospholipids of the cell membrane. The dye molecules are phosphorescent transition metal polypyridine complexes having a metal center and ligands which are non-organic fluorophores.

Abstract: A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is formed on the top surface and a plurality of first conductive terminals are formed on the recess. Further, a plurality of second conductive terminals are formed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is formed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.

Abstract: The present invention is concerned with a staining dye for staining a biological cell, comprising dye molecules with a positively charged polar head group for attraction to cell membrane of the cell and for refraining the dye molecules from entering the cytoplasm, and one or more hydrophobic groups for interaction with phospholipids of the cell membrane. The dye molecules are phosphorescent transition metal polypyridine complexes having a metal center and ligands which are non-organic fluorophores.

Abstract: An optoelectronic apparatus is described herein, including a transmitter, a receiver, and an optical waveguide, all of which are embedded in a PCB. The transmitter includes a laser generator and other circuits for generating electrical and optical signals, which are transmitted through the waveguide to the receiver. The receiver includes circuits and detectors for detecting and converting the optical signals to electrical signals. The circuit and optical components of the transmitter and receiver are integrated in 3D hybrid chip sets where the chip components are stacked in a 3D structure. Because all of the circuit and optical components are embedded in the PCB, the apparatus is made very compact and suitable for implementation in portable products.

Abstract: An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat.

Abstract: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.

Abstract: A packaging substrate includes a carrier and an interposer. The carrier has opposite top and bottom surfaces. A recess is formed on the top surface and a plurality of first conductive terminals are formed on the recess. Further, a plurality of second conductive terminals are formed on the bottom surface of the carrier. The interposer is disposed in the recess and has opposite first and second surfaces and a plurality of conductive through vias penetrating the first and second surfaces. A first conductive pad is formed on an end of each of the conductive through vias exposed from the first surface, and a second conductive pad is formed on the other end of each of the conductive through vias exposed from the second surface and electrically connected to a corresponding one of the first conductive terminals. Compared with the prior art, the invention improves the product reliability.

Abstract: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.

Abstract: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.

Abstract: In some embodiments, a logic circuit is provided that has a plurality of gates with gate inputs. Also provided is one or more latch circuits coupled to the logic circuit to provide operational data when in an operational mode and to cause at least some of the gate inputs to be at values resulting in reduced leakage during a sleep mode. Additionally provided are embodiments of non-destructive latch circuits, which may be used to implement the latch circuits just discussed. Other embodiments are disclosed and/or claimed herein.

Abstract: An optoelectronic apparatus is described herein, including a transmitter, a receiver, and an optical waveguide, all of which are embedded in a PCB. The transmitter includes a laser generator and other circuits for generating electrical and optical signals, which are transmitted through the waveguide to the receiver. The receiver includes circuits and detectors for detecting and converting the optical signals to electrical signals. The circuit and optical components of the transmitter and receiver are integrated in 3D hybrid chip sets where the chip components are stacked in a 3D structure. Because all of the circuit and optical components are embedded in the PCB, the apparatus is made very compact and suitable for implementation in portable products.

Abstract: An apparatus having a three-dimensional integrated circuit structure is described herein. The apparatus include an interposer for carrying a plurality of high and low-power chips. The high-power chips are attached and connected to one side of the interposer, while the low-power chips are attached and connected to the other side of the interposer. In generally, the high-power chips produce more heat than does the low-power chip during their operations. The interposer further include through silicon vias and redistribution layers for connecting the chips on both surfaces. In addition, the interposer assembly is attached and connected to a substrate layer, which is in turn attached and connected to a printed circuit board. In order to provide improve thermal management, the interposer surface carrying the high-power chips are oriented away from the circuit board. A heat spreader is attached to the back sides of the high-power chips for dissipating the heat.

Abstract: In one embodiment, the present invention includes a method for receiving first and second data operands in a common execution unit and manipulating the operands responsive to an instruction to generate an output according to local control signals of a local controller of the execution unit. Various instruction types such as shuffle and shift operations may be performed in the common execution unit in a single cycle. Other embodiments are described and claimed.

Abstract: In one embodiment, the present invention includes a method for receiving first and second data operands in a common execution unit and manipulating the operands responsive to an instruction to generate an output according to local control signals of a local controller of the execution unit. Various instruction types such as shuffle and shift operations may be performed in the common execution unit in a single cycle. Other embodiments are described and claimed.

Abstract: A pin tumbler lock, operating between a locked position and a released position, comprising a first lock member having at least one first bore with a biasing device and a first pin deposing in the first bore, and a second lock member engaging with the first lock member, forming an interface surface with said first lock member. The second lock member has at least one second bore with a second pin disposed in the second bore, and is aligned with the first bore for receiving the first pin in the locked position. At least one pin is magnetized, and the corresponding second pin is magnetic permeable, such that, when the pins are mobilized by an external force, the magnetized pin remains attracted to the corresponding magnetic permeable pin. No open space between the pins is formed at the interface surface to release the lock members.