Abstract: A slider row bar de-bond fixture has a base plate; a row of separator walls formed on a top surface of the base plate and spaced one another for separating a plurality of slider row bars; and a plurality of grooves defined between the adjacent separator walls for receiving the slider row bars respectively. Each of the separator walls has a free top end with a smaller depth than its bottom end. Preferably, each of the separator walls has a structure of trapezoid or triangular form in cross section. The slider row bar de-bond fixture occupy a little room and more importantly, receive the debonded slider row bars more safely and without overlapping.

Abstract: An add-on kit comprising a (1) ring of (2) magnets (easy to install) is installed onto a (6) wheel of bike or car. An arrangement of (3) electromagnets and (5) inductors (detectors) is installed onto the (4) fork of a bike or suspension of car in the proximity of the ring. By turning the (3) electromagnets on and off and controlling the on-time and the field strength, a force that assists the wheel in rotating is produced. With the electromagnets turned-off, the moving ring of permanent magnets also provides for regenerative braking. With the bicycle mounted on an elevated stand, and the controlled timing of the electromagnets programmed to induce a force in the backwards direction, a user can use his bike as an exercise machine, gaming/training apparatus, or just to recharge the batteries.

Abstract: A process for characterizing defects in semiconductors or insulators using a zero-bias thermally stimulated current technique wherein parasitic current is eliminated by the use of a novel ZBTSC apparatus that eliminates temperature gradient across a sample is described. The novel ZBTSC apparatus comprises a cold finger on a cyrostat. A sample holder is attached to the cold finger. A probe holder is attached to the cold finger. A probe is attached to the probe holder. A feedback temperature control keeps the probe and the cold finger at the same temperature. The improved zero-bias thermally stimulated current technique of the invention comprises mounting a sample on the sample holder of the novel ZBTSC apparatus. The sample is excited at a first temperature to fill up defect traps with carriers and then heated to a second temperature higher than the first temperature wherein the heating is a linear function with respect to time.

Abstract: A process for characterizing defects in semiconductors or insulators using a zero-bias thermally stimulated current technique wherein parasitic current is eliminated by the use of a novel ZBTSC apparatus that eliminates temperature gradient across a sample is described. The novel ZBTSC apparatus comprises a cold finger on a cyrostat. A sample holder is attached to the cold finger. A probe holder is attached to the cold finger. A probe is attached to the probe holder. A feedback temperature control keeps the probe and the cold finger at the same temperature. Alternatively, the sample holder may be attached to a first cold finger and the probe holder attached to a second cold finger. Feedback temperature controls for each cold finger are programed such that their temperatures are kept the same. The improved zero-bias thermally stimulated current technique of the invention comprises mounting a sample on the sample holder of the novel ZBTSC apparatus.

Abstract: A method of fabricating a metal-oxide-metal (MOM) capacitor, comprising the following steps. A bottom metal layer is deposited. A high dielectric constant oxide insulator is deposited layer over the bottom metal layer. The structure is annealed in an oxidizing ambient to cause the exposed bottom metal to form a metal oxide partially filling the one or more pin hole defects to repair those pin hole defects. An upper oxide conductor layer is then deposited over the high dielectric constant oxide insulator layer. An upper metal layer is deposited over said upper oxide conductor layer.

Abstract: This invention describes a method to test both auto-refresh and self refresh of an SDRAM. The method writes a logical zero in to a single cell on each word line using a write with auto-precharge and increments an internal counter with either auto-refresh or self refresh to select the row address. The test is performed using existing circuitry on the SDRAM, and when testing self refresh, the refresh cycle is exited shortly after a cell on a row has been written into so as to not run the entire refresh cycle and save test time. A test signature is formed by the logical zeros written into one cell along each word line. Comparing this signature with the signature that should exist provides an easy way to determine if there is a test error and where the error occurred.

Abstract: A power down system for regulated internal power supply in DRAM comprises a RAS control module, self-refresh clock control circuit, and a power down control circuit. The RAS control module responds with row address strobe signals to output a first power down control signal. While all the row address strobe signals, which denote states of the memory banks, are in a first condition of inactivity, the first power down control signal will inform the power down system to turn off a regulator in the DRAM under the first condition. The self-refresh clock control circuit responds with a self-refresh clock to output a second power down control signal. While the self-refresh clock is in a second condition of non-self-refresh mode, the second power down control signal will inform the power down system to turn off the regulator under the second condition.

Abstract: A semiconductor memory device with a function of equalizing voltages of dataline pair. After turning off the word line and before turning on the equalization means, the datalines are precharged and discharged to a supplied voltage and ground, respectively. Using the theory of uniform distribution of charges, the datalines are equalized into VCC/2, that is, a half of the source supply voltage. The interference on a weak voltage VCC/2 generator within the equalization means during the equalization mode is thus avoided. The equalization of voltages on the dataline pair can be achieved within a transient cycle. Complete data can thus be written or read before the next command is given.

Abstract: A dynamic precharge redundant circuit for a semiconductor memory device. A PMOS transistor, a fuse, a first, second and third inverters, a first switch and a second switch are applied. A source of the PMOS transistor is coupled to a voltage supply, while a gate of the PMOS transistor is to receive a precharge signal. The fuse has a ground terminal and a terminal coupled to the drain of the PMOS transistor of which the drain is further coupled to an input terminal of the first inverter. The fuse is also coupled to a column address signal. The first inverter has an output terminal coupled to an input terminal of the first switch. The second inverter has an input terminal coupled to an output terminal of the first switch and an output terminal coupled to an input terminal of the third inverter, so as to output a bit-switch control signal.

Abstract: A power down scheme for a regulated sense amplifier power in DRAM. The power-supply level voltage Vccsa of a sense amplifier is turned on only within a certain time duration, which has no relationship with the word line turn-on time. The power down scheme includes control logic gates and time delay circuits which can be triggered by two internal control signals from other control modules in order to generate a power-down control signal for the bit line sense amplifier.

Abstract: This invention describes a biasing scheme that reduces burn-in testing time as well as the number of cycles through the burn-in test for a semiconductor memory. The magnitude of a substrate back bias is reduced when a semiconductor memory device is taken into burn-in at a first value of an external applied voltage. When the memory device is brought out of burn-in, the substrate back bias is returned to the original operating level at a second value of the external applied voltage. The reduction of the substrate back bias allows for a higher external voltage to stress the semiconductor memory without forcing breakdown and results in a shorter test time. The burn-in test is entered at a higher magnitude of the external applied voltage than the voltage at which burn-in testing is exited. This helps to reduce the number of cycles through the burn-in test by providing a stronger external bias.

Abstract: An adder using a leading zero/one detector (LZD) circuit and method of use determine an exact normalization shift with fewer logic levels and number of gates, resulting in saving considerable execution time to improve not only the timing as well as to reduce the size of the logic implementing the adder. In addition, a parallel method to locate the most significant digit is disclosed. Such an LZD circuit and method may be incorporated in an integrated circuit, and the LZD circuit includes a propagation value generator for generating a propagation value from input signals representing operands; and a location value generator for generating the location value from the generated propagation value.

Abstract: An integrated circuit having a fast carry generation adder for adding together two input signals has an initial stage and two or more intermediate stages. The adder may also include a final stage. Each intermediate stage has a carry mux and these carry muxes are grouped together, for example, adjacent to the initial stage and adjacent to the first intermediate stage. By grouping the carry muxes together, for example, in a column below the initial stage, the fast carry generation adder may be both faster and smaller than conventional adders and may reduce or even eliminate the need for any buffering between successive carry muxes.

Abstract: An integrated circuit including a circuit for determining shift overflow in a binary digital circuit having an n-bit shift data and an m-bit shift amount. The device has a logic array for producing an n-bit output from the m-bit shift amount; a conversion circuit for selectively converting the sign of an n-bit shift data; and a combination of OR and AND logical gates for logically combining the selectively converted n-bit shift data and the n-bit output producing an overflow output.

Abstract: A system for selectively controlling individual expansion slots in an IBM-AT/NEC 9801 dual compatible computer provides automatic control for the individual ISA bus expansion slots in the computer. This facilitates the use of an Industry Standard Architecture (ISA) bus and ISA (AT) type add-on cards in the dual compatible computer. A user configures each slot as containing either a card which may interfere with operations of the computer in the non-IBM-AT compatible mode or a card which will not interfere with computer operations in the non-IBM-AT compatible mode. Thereafter, the computer automatically disables the cards in accordance with the mode of computer operation.