Patents by Inventor Shing-Yih Shih

Shing-Yih Shih has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12100634
    Abstract: The present application discloses a semiconductor device with a re-fill layer. The semiconductor device includes a chip stack including a first base die; a first stacked die positioned on a front surface of the first base die; and a re-fill layer positioned on a sidewall of the stacked die. The re-fill layer includes silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, titanium oxide, aluminum oxide, or hafnium oxide.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: September 24, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Publication number: 20240234249
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a first substrate, having a front side and a back side opposite to the front side; a first passivation layer over the front side of the first substrate; a second passivation layer over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate; a conductive feature disposed in the first passivation layer; a through substrate via penetrating through the second passivation layer and the first substrate; and a polymer liner between a sidewall of the through substrate via and the first substrate.
    Type: Application
    Filed: January 6, 2023
    Publication date: July 11, 2024
    Inventor: SHING-YIH SHIH
  • Publication number: 20240234252
    Abstract: The present disclosure provides a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a first substrate, having a front side and a back side opposite to the front side; a first passivation layer over the front side of the first substrate; a second passivation layer over the back side of the first substrate, wherein the second passivation layer has a top surface facing away from the first substrate; a conductive feature disposed in the first passivation layer; a through substrate via penetrating through the second passivation layer and the first substrate; and a polymer liner between a sidewall of the through substrate via and the first substrate.
    Type: Application
    Filed: October 16, 2023
    Publication date: July 11, 2024
    Inventor: SHING-YIH SHIH
  • Publication number: 20240178189
    Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.
    Type: Application
    Filed: February 7, 2024
    Publication date: May 30, 2024
    Inventor: Shing-Yih Shih
  • Publication number: 20240153902
    Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.
    Type: Application
    Filed: September 13, 2023
    Publication date: May 9, 2024
    Inventors: SHENG-FU HUANG, SHING-YIH SHIH
  • Publication number: 20240153900
    Abstract: A semiconductor device structure and method for manufacturing the same are provided. The semiconductor device structure includes a substrate, a dielectric structure, a pad, a conductive structure, and a buffer structure. The dielectric structure is disposed on the substrate. The pad is embedded in the dielectric structure. The conductive structure is disposed on the pad. The buffer structure is disposed on the pad and separates the conductive structure from the dielectric structure. A coefficient of thermal expansion (CTE) of the buffer structure ranges between a CTE of the dielectric structure and a CTE of the conductive structure.
    Type: Application
    Filed: November 7, 2022
    Publication date: May 9, 2024
    Inventors: SHENG-FU HUANG, SHING-YIH SHIH
  • Publication number: 20240153878
    Abstract: The present application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and comprising a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and comprising a second cache unit. The first redistribution structure comprises: a plurality of conductive layers electrically coupled the first die and the first cache unit of the second die and electrically coupled the first die and the second cache unit of the third die, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit of the second die and the second cache unit of the third die are topographically aligned with the first die.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventor: SHING-YIH SHIH
  • Publication number: 20240153879
    Abstract: The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and including a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and including a second cache unit. The first redistribution structure includes: a plurality of conductive layers electrically coupled the first die and the first cache unit and electrically coupled the first die and the second cache unit, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit and the second cache unit are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.
    Type: Application
    Filed: September 13, 2023
    Publication date: May 9, 2024
    Inventor: SHING-YIH SHIH
  • Patent number: 11935831
    Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a first semiconductor structure; and forming a first connecting structure comprising a first connecting insulating layer on the first semiconductor structure, a plurality of first connecting contacts in the first connecting insulating layer, and a plurality of first supporting contacts in the first connecting insulating layer.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: March 19, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11935816
    Abstract: The present disclosure provides a semiconductor device, a semiconductor assembly and method of manufacturing the semiconductor assembly. The semiconductor device includes a substrate, a conductive feature in the substrate, an isolation liner between the substrate and the conductive feature, and a main component in the substrate. The conductive feature includes first to third blocks. The first block has a uniform first critical dimension, wherein the main component is disposed around the first block. The second block has a uniform second critical dimension greater than the first critical dimension. The third block is interposed between the first block and the second block and has varying third critical dimensions.
    Type: Grant
    Filed: June 14, 2022
    Date of Patent: March 19, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Shing-Yih Shih, Jheng-Ting Jhong
  • Patent number: 11901344
    Abstract: A manufacturing method of a semiconductor package is provided as follows. A semiconductor die is provided, wherein the semiconductor die comprises a semiconductor substrate, an interconnection layer and a through semiconductor via, the interconnection layer is disposed on an active surface of the semiconductor substrate, the through semiconductor via penetrates the semiconductor substrate from a back surface of the semiconductor substrate to the active surface of the semiconductor substrate. An encapsulant is provided to laterally encapsulate the semiconductor die. A through encapsulant via penetrating through the encapsulant is formed.
    Type: Grant
    Filed: October 21, 2021
    Date of Patent: February 13, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11901334
    Abstract: A semiconductor package includes a resin molded package substrate comprising a resin molded core, a plurality of metal vias in the resin molded core, a front-side RDL structure, and a back-side RDL structure. A bridge TSV interconnect component is embedded in the resin molded core. The bridge TSV interconnect component has a silicon substrate portion, an RDL structure integrally constructed on the silicon substrate portion, and TSVs in the silicon substrate portion. A first semiconductor die and a second semiconductor die are mounted on the front-side RDL structure. The first semiconductor die and the second semiconductor die are coplanar.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: February 13, 2024
    Assignee: Micron Technology, Inc.
    Inventor: Shing-Yih Shih
  • Publication number: 20240047395
    Abstract: A semiconductor structure includes a first chip and a second chip bonded to the first chip. The first chip includes a first semiconductor substrate, a first multi-level interconnect structure over the first semiconductor substrate, a first redistribution layer (RDL) over a conductive line of the first multi-level interconnect structure, a compact layer over the first RDL and the first multi-level interconnect structure, a cap layer over the compact layer, and a metal pad on the first RDL. The second chip includes a second semiconductor substrate, a second multi-level interconnect structure over the second semiconductor substrate, and conductive structure extending from the second multi-level interconnect structure to the metal pad.
    Type: Application
    Filed: August 8, 2022
    Publication date: February 8, 2024
    Inventors: Sheng-Fu HUANG, Shing-Yih SHIH
  • Publication number: 20240047394
    Abstract: A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 8, 2024
    Inventor: SHING-YIH SHIH
  • Publication number: 20240021527
    Abstract: The present application provides a semiconductor package structure having interconnections between dies, and a manufacturing method of the semiconductor package structure. The semiconductor package structure includes a first interposer including a first substrate and a first interconnect layer over the first substrate; a second interposer disposed over the first interposer, wherein the second interposer includes a second substrate and a second interconnect layer over the second substrate; a first die disposed over the first interposer and adjacent to the second interposer; a second die disposed over the second interposer; a first molding disposed over the second interposer and surrounding the second die; and a second molding disposed over the first interposer and surrounding the first die and the first molding, wherein the first interconnect layer includes a first communication member electrically connecting the first die to the second interposer and the second die.
    Type: Application
    Filed: July 14, 2022
    Publication date: January 18, 2024
    Inventor: SHING-YIH SHIH
  • Publication number: 20240021528
    Abstract: The present application provides a semiconductor package structure having interconnections between dies, and a manufacturing method of the semiconductor package structure. The semiconductor package structure includes a first interposer including a first substrate and a first interconnect layer over the first substrate; a second interposer disposed over the first interposer, wherein the second interposer includes a second substrate and a second interconnect layer over the second substrate; a first die disposed over the first interposer and adjacent to the second interposer; a second die disposed over the second interposer; a first molding disposed over the second interposer and surrounding the second die; and a second molding disposed over the first interposer and surrounding the first die and the first molding, wherein the first interconnect layer includes a first communication member electrically connecting the first die to the second interposer and the second die.
    Type: Application
    Filed: May 12, 2023
    Publication date: January 18, 2024
    Inventor: SHING-YIH SHIH
  • Patent number: 11876063
    Abstract: A semiconductor package structure includes a first semiconductor wafer including a first bonding pad. The semiconductor package structure also includes a second semiconductor wafer including a second bonding pad and a third bonding pad. The second bonding pad and the third bonding pad are bonded to the first bonding pad of the first semiconductor wafer. The semiconductor package structure further includes a first via penetrating through the second semiconductor wafer to physically contact the first bonding pad of the first semiconductor wafer. A portion of the first via is disposed between the second bonding pad and the third bonding pad.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: January 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Patent number: 11876079
    Abstract: The provides a method for fabricating a semiconductor device including performing a bonding process to bond a second die onto a first die including a pad layer, forming a through-substrate opening along the second die and extending to the pad layer in the first die, conformally forming an isolation layer in the through-substrate opening, performing a punch etch process to remove a portion of the isolation layer and expose a portion of a top surface of the pad layer, performing an isotropic etch process to form a recessed space extending from the through substrate opening and in the pad layer, conformally forming a barrier layer in the through-substrate opening and the recessed space, and forming a filler layer in the through-substrate opening and the recessed space.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: January 16, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Shing-Yih Shih
  • Publication number: 20240014089
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a first substrate, a first dielectric layer disposed on the first substrate, a first passivation layer disposed on the first dielectric layer, a second substrate disposed on the first passivation layer, and a second substrate disposed on the first passivation layer. The semiconductor structure further includes a first seal ring embedded within the first dielectric layer and surrounds a circuit region of the first dielectric layer. The semiconductor structure further includes a thermal conductive structure embedded within the first passivation layer, wherein the thermal conductive structure is connected with the first seal ring through a first connecting structure.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 11, 2024
    Inventor: SHING-YIH SHIH
  • Publication number: 20240014048
    Abstract: A method of manufacturing a semiconductor structure is provided. The method includes forming a thermal conductive structure embedded within a first passivation layer of a first wafer, and forming a plurality of conductive vias penetrating a first substrate of the first wafer and in contact with the thermal conductive structure. The method further includes forming a first connecting structure in contact with the thermal conductive structure and exposed by a surface of the first passivation layer. The method further includes bonding the first connecting structure of the first wafer to a second connecting structure of a second wafer, and bonding the first passivation layer of the first wafer to a first dielectric layer of the second wafer, wherein a first seal ring embedded within the first dielectric layer of the second wafer is thermally connected to the thermal conductive structure through the first connecting structure and the second connecting structure.
    Type: Application
    Filed: July 5, 2022
    Publication date: January 11, 2024
    Inventor: SHING-YIH SHIH