Abstract: A rail insert is disclosed. The rail insert includes a backing member, at least one locating pin connected to the backing member, and at least one locking pin connected to the backing member. The backing member has a rail side and a grip side. The at least one locking pin has at least one compressible member.

Abstract: The disclosure is related to a system and a method for collision avoidance for vehicle. In the method, the system predicts multiple routes of an abnormal vehicle in a period of time according to historical data when a nearby vehicle receives an alert from the abnormal vehicle. A route potential pattern can be created when the system gets the historical data. The system also computes one or more available routes for the nearby vehicle based on its vehicle information. Every available route has its collision risk value. The system finally provides a recommended route with lower collision risk value when it considers a time of the abnormal vehicle reaches its great change, a time of predicting the nearby vehicle meets the range of route potential pattern, and a safe distance there-between.

Abstract: The disclosure is related to a system and a method for collision avoidance for vehicle. In the method, the system predicts multiple routes of an abnormal vehicle in a period of time according to historical data when a nearby vehicle receives an alert from the abnormal vehicle. A route potential pattern can be created when the system gets the historical data. The system also computes one or more available routes for the nearby vehicle based on its vehicle information. Every available route has its collision risk value. The system finally provides a recommended route with lower collision risk value when it considers a time of the abnormal vehicle reaches its great change, a time of predicting the nearby vehicle meets the range of route potential pattern, and a safe distance there-between.

Abstract: A clock and data recovery circuit includes a sampling module, a phase detect module, a parallel-to-serial converter and a phase adjust module. The sampling module generates a data signal and an edge signal according to input data, a first clock signal and a second clock signal. The phase detect module detects a phase of the data signal and a phase of the edge signal to generate first output recovered data and a first phase adjust signal. The parallel-to-serial converter performs a parallel-to-serial conversion on the first recovered data and the first phase adjust signal, so as to generate second output recovered data and a second phase adjust signal. The phase adjust module generates the first clock signal and the second clock signal, and adjusts the first clock signal and the second clock signal according to the second output recovered data and the second phase adjust signal.

Abstract: The present invention discloses pre-amplifier with a selectable threshold voltage in a decision feedback equalization circuit to reduce tap weight variation. A decision feedback equalization circuit includes a summer circuit and a pre-amplifier with an offset generator, wherein the pre-amplifier includes a pair of differential amplifiers and each biased by a respective current bias and each having first and second output nodes coupled to a supply voltage via a respective resistive element, R. The resistive elements may be implemented, for example, using diode-configured transistors, biased transistors, resistor, or any other active or passive circuitry for establishing a resistance. The inputs of first differential amplifier are coupled to the summer's output. The inputs of second differential amplifier are coupled to a reference voltage circuit that comprised of a resistive element and a respective current DAC (IDAC).

Abstract: A dock and data recovery circuit includes a sampling module, a phase detect module, a parallel-to-serial converter and a phase adjust module. The sampling module generates a data signal and an edge signal according to input data, a first dock signal and a second dock signal. The phase detect module detects a phase of the data signal and a phase of the edge signal to generate first output recovered data and a first phase adjust signal. The parallel-to-serial converter performs a parallel-to-serial conversion on the first recovered data and the first phase adjust signal, so as to generate second output recovered data and a second phase adjust signal. The phase adjust module generates the first clock signal and the second clock signal, and adjusts the first clock signal and the second clock signal according to the second output recovered data and the second phase adjust signal.

Abstract: A gated voltage-controlled oscillator receives a gating signal and outputs an oscillating signal having a frequency corresponding to the gating signal. The gated voltage-controlled oscillator includes a delay unit, having a first terminal and a second terminal, and a multiplexer, having a first input terminal, a second input terminal, a select terminal and an output terminal. The first input terminal and the select terminal are coupled to the gating signal. The second input terminal is coupled to the first terminal of the delay unit. The output terminal outputs the oscillating signal and is coupled to the second terminal of the delay unit. The delay unit delays the oscillating signal and outputs the delayed oscillating signal into the second input terminal. The multiplexer outputs a signal of the first input terminal or the second input terminal according to the gating signal.

Abstract: The invention provides a clock and data recovery (CDR) circuit, including a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal according to a control signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.

Abstract: The invention provides a clock and data recovery (CDR) circuit, including: a phase locked loop (PLL) circuit, providing a reference voltage; a first delay device, delaying an input data according to a control signal so as to generate a first delay signal; an edge detector, generating an edge signal according to the first delay signal and the input data; a second delay device, delaying the edge signal so as to generate a second delay signal; a first gated voltage-controlled oscillator, generating an output recovery clock according to the second delay signal and the reference voltage; a phase detector, detecting a phase difference between the first delay signal and the output recovery clock so as to generate a phase signal and a output recovery data; and an amplifier, amplifying the phase signal by a factor so as to generate the control signal.

Abstract: A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node.

Abstract: An apparatus and method are disclosed to implement a universal 3D (3-Dimensional) image system with automatic search for 3D communication protocol. The apparatus includes a memory to store a plurality of communication protocols. The apparatus further includes a controller operatively coupled to the memory to detect a transmitted communication protocol by comparing the transmitted communication protocol with the plurality of communication protocols stored in the memory of the glasses. In addition, the controller receives and processes the 3D image data based on the transmitted communication protocol.

Abstract: A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node.

Abstract: A computer platform memory access control method and system is proposed, which is designed for use with a computer platform, such as a network server, for providing the server with a memory access control function with a memory configuration automatic setting capability, which is characterized by the arrangement of a configuration data exchange path between a memory control chip and an I/O control chip on the server's motherboard, so as to allow a set of memory specification data stored in an I/O configuration register of the ICH I/O control chip to be mapped via the configuration data exchange path to a memory configuration register of the memory control chip, such that a memory access action can be performed based on the memory specification data mapped from the I/O control chip. This feature allows the operation and network management of servers to be made more efficient.

Abstract: A computer platform memory access control method and system is proposed, which is designed for use with a computer platform, such as a network server, for providing the server with a memory access control function with a memory configuration automatic setting capability, which is characterized by the arrangement of a configuration data exchange path between a memory control chip and an I/O control chip on the server's motherboard, so as to allow a set of memory specification data stored in an I/O configuration register of the ICH I/O control chip to be mapped via the configuration data exchange path to a memory configuration register of the memory control chip, such that a memory access action can be performed based on the memory specification data mapped from the I/O control chip. This feature allows the operation and network management of servers to be made more efficient.

Abstract: A method for treating or preventing infarction of a patient comprising administering a hepsin antagonist with a dosage effective to suppress or inactivate hepsin's expression over a sustained period.

Abstract: An immersion lithography system is disclosed to comprise a fluid containing feature for providing an immersion fluid for performing immersion lithography on a wafer, and a seal ring covering a predetermined portion of a wafer edge for preventing the immersion fluid from leaking through the covered portion of the wafer edge while the fluid is used for the immersion lithography.