Abstract: When a prescribed operation is performed on 1024-bit multiple-precision data in a data-driven processor, the multiple-precision data is treated as a plurality of single-precision data obtained by dividing the multiple-precision data by every 32 bits in accordance with the memory word length of an accumulation memory, and a group of 32 memory words each having 32 bits of the accumulation memory is treated as the multiple-precision data. Accordingly, in the data-driven processor, a usual memory region can serve as an accumulator for multiple-precision data without having to provide any accumulator dedicated to multiple-precision data in the data-driven processor. In addition, since the multiple-precision data is divided into independent single-precision data each having 32 bits, operations for all data can be performed concurrently. Thus, a parallel processing capability of the data-driven processor can be maximized.

Abstract: When the cache memory unit reads the last word of a page of the cache memory, the external memory interface reads ahead data of a prescribed number of pages ahead of the relevant page. Thus, data corresponding to the access request to the external main memory is always held in the cache memory. This prevents degradation of parallel processing capability of the data driven type information processing apparatus.

Abstract: In order to perform functional packet copying to read a large amount of data of an unspecified length from a memory at high speed and to prevent the packet copying operation from affecting other packet flow, a self-synchronous transfer control circuit having a function of controlling transfer operation is used, by which the number of packet copies output from a data holding register is managed by a counter, and the number of copies represented by the copy request packet and the counter count value are compared by a comparator, to determine completion of the packet copying operation.

Abstract: An execution control apparatus of a data driven information processor includes: an instruction decoder that outputs the number of inputs of an instruction; a waiting data storage region that stores N(N≧2) waiting data and respective data valid flags in one address; a constant storage that stores constants and a constant valid flag; a constant readout unit that reads out a constant and a constant valid flag from the constant storage with the node number of the packet as the address; a unit that calculates the address and selects a process for data waiting depending upon a combination of a data valid flag, a constant valid flag, and the number of instruction inputs; and a unit that performs the waiting process in response to the select signal.

Abstract: When a prescribed operation is performed on 1024-bit multiple-precision data in a data-driven processor, the multiple-precision data is treated as a plurality of single-precision data obtained by dividing the multiple-precision data by every 32 bits in accordance with the memory word length of an accumulation memory, and a group of 32 memory words each having 32 bits of the accumulation memory is treated as the multiple-precision data. Accordingly, in the data-driven processor, a usual memory region can serve as an accumulator for multiple-precision data without having to provide any accumulator dedicated to multiple-precision data in the data-driven processor. In addition, since the multiple-precision data is divided into independent single-precision data each having 32 bits, operations for all data can be performed concurrently. Thus, a parallel processing capability of the data-driven processor can be maximized.