Patents by Inventor Shingo Sato

Shingo Sato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12661689
    Abstract: A method for forming a multilayer film, including: a step (1) of applying an aqueous two-pack first colored coating material on an automobile outer panel to form an uncured first colored coating film; a step (2) of applying an aqueous one-pack white color coating material on the uncured first colored coating film to form an uncured white coating film; a step (3) of setting the uncured white coating film for 4 minutes or more such that a resultant coating film has a solid content of 50% by mass or more; a step (4) of applying an aqueous one-pack interference color coating material on the uncured white coating film having the solid content of 50% by mass or more to form an uncured interference color coating film; a step (5) of applying a solvent-based two-pack clear coating material on the uncured interference color coating film to form an uncured clear coating film; and a step (6) of heating the coating films formed in the steps (1) to (5) at a temperature of 75° C. or more and to 100° C.
    Type: Grant
    Filed: June 6, 2023
    Date of Patent: June 23, 2026
    Assignees: KANSAI PAINT CO., LTD., NISSAN MOTOR CO., LTD.
    Inventors: Shingo Sato, Mutsumi Yamazaki, Yuko Iwara, Tatsuya Suzuki, Hironori Tsutsui
  • Publication number: 20260090043
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, second semiconductor regions of a second conductivity type, a third semiconductor region of the second conductivity type, a fourth semiconductor region of the first conductivity type, a gate electrode, fifth semiconductor regions of the second conductivity type, sixth semiconductor regions of the second conductivity type, and a second electrode. The fifth semiconductor regions are arranged with the second semiconductor regions in a second direction. A distance between two of the fifth semiconductor regions adjacent to each other is longer than a distance between two of the second semiconductor regions adjacent to each other. The sixth semiconductor regions are provided in the second portion. The sixth semiconductor regions are arranged with the second semiconductor regions in a third direction.
    Type: Application
    Filed: January 31, 2025
    Publication date: March 26, 2026
    Inventor: Shingo SATO
  • Publication number: 20250360536
    Abstract: A method for forming a multilayer film, including: a step (1) of applying an aqueous two-pack first colored coating material on an automobile outer panel to form an uncured first colored coating film; a step (2) of applying an aqueous one-pack white color coating material on the uncured first colored coating film to form an uncured white coating film; a step (3) of setting the uncured white coating film for 4 minutes or more such that a resultant coating film has a solid content of 50% by mass or more; a step (4) of applying an aqueous one-pack interference color coating material on the uncured white coating film having the solid content of 50% by mass or more to form an uncured interference color coating film; a step (5) of applying a solvent-based two-pack clear coating material on the uncured interference color coating film to form an uncured clear coating film; and a step (6) of heating the coating films formed in the steps (1) to (5) at a temperature of 75° C. or more and to 100° C.
    Type: Application
    Filed: June 6, 2023
    Publication date: November 27, 2025
    Applicants: KANSAI PAINT CO., LTD., NISSAN MOTOR CO., LTD.
    Inventors: Shingo SATO, Mutsumi YAMAZAKI, Yuko IWARA, Tatsuya SUZUKI, Hironori TSUTSUI
  • Patent number: 12473605
    Abstract: A method for producing low-carbon ferromanganese capable of achieving a high Mn yield. In producing low-carbon ferromanganese by blowing an oxidizing gas from a top-blowing lance onto a bath face of high-carbon ferromanganese molten metal accommodated in a reaction vessel provided with a top-blowing lance and bottom-blowing tuyere to perform decarburization, the slag composition during the blowing is adjusted so that a value of (CaO+MgO)/(Al2O3+SiO2) on a mass basis in the slag composition is not less than 0.4 but not more than 5.0. Also, agitation is performed under a condition that an agitation power density ? of an agitation gas blown through the bottom-blowing tuyere is not less than 500 W/t.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: November 18, 2025
    Assignees: JFE STEEL CORPORATION, JFE MINERAL & ALLOY COMPANY, LTD.
    Inventors: Nobuhiko Oda, Yusuke Fujii, Shingo Sato, Ryo Kawabata, Naoki Kikuchi, Toshio Shiota, Ippei Higuchi
  • Patent number: 12439675
    Abstract: According to one embodiment, a semiconductor device includes first to third electrodes, a semiconductor member, a first conductive member, a connecting member, a first member, and an insulating member. The semiconductor member includes first to third semiconductor regions. The first semiconductor region is between the first electrode and the third semiconductor region. The first semiconductor region includes first to third partial regions. The second semiconductor region is between the first and third semiconductor regions. The second semiconductor region includes third and fourth semiconductor portions. The third semiconductor region includes first and second semiconductor portions. The second electrode is electrically connected with the third semiconductor region. The third electrode includes a first electrode portion. The first conductive member includes first to third conductive regions. The connecting member is electrically connected with the first conductive member.
    Type: Grant
    Filed: June 29, 2022
    Date of Patent: October 7, 2025
    Assignees: KABUSHIKI KAISHA TOSHIBA, TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION
    Inventors: Shotaro Baba, Hiro Gangi, Hiroaki Katou, Saya Shimomura, Shingo Sato
  • Patent number: 12432967
    Abstract: A semiconductor device includes: a semiconductor part including a first semiconductor layer and a second semiconductor layer in contact with the first semiconductor layer; a first electrode electrically connected to the first semiconductor layer on a front surface side or a back surface side of the semiconductor part; a second electrode electrically connected to the second semiconductor layer on the front surface side of the semiconductor part; a gate electrode; an interlayer insulating film electrically insulating the gate electrode and the second electrode on the front surface side of the semiconductor part; and a third semiconductor layer having: a first region in contact with the second semiconductor layer and the second electrode on the front surface side of the semiconductor part; and a second region provided between the interlayer insulating film and the second electrode in a second direction perpendicular to a first direction.
    Type: Grant
    Filed: February 21, 2023
    Date of Patent: September 30, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Yuhki Fujino, Tsuyoshi Kachi, Katsura Miyashita, Shingo Sato
  • Publication number: 20250264500
    Abstract: [Problem] To prevent a flexible wiring board from peeling off from a substrate. [Solution] This probe card comprises: a substrate 30 having a flat surface that faces an object 20 to be tested; a flexible wiring board 50 which is composed of an insulating film 51 and has an adhesive surface adhered to the substrate 30 via an adhesive agent 40 and a probe mounting surface on which two or more electrode pads 520 are aligned and arranged at a predetermined interval; and two or more probes 70 respectively disposed on the electrode pads 520. Two or more first anchor pads 521 are respectively formed at positions on the adhesive surface that correspond to the electrode pads 70.
    Type: Application
    Filed: July 1, 2022
    Publication date: August 21, 2025
    Applicant: JAPAN ELECTRONIC MATERIALS CORPORATION
    Inventors: Keiji MATSUOKA, Shingo SATO, Tomoaki INOUE
  • Patent number: 12312574
    Abstract: There has been demand for an additional method for producing antibodies. The present invention provides: a polymer-coated crosslinked alginate gel fiber in which a core layer containing a crosslinked alginate gel and either antibody-producing cells (e.g., antibody-producing CHO cells) or bioactive-substance-producing cells (e.g., MIN6 cells derived from pancreatic ? cells) is coated with a cationic polymer; and a method for producing antibodies, a bioactive substance, etc., using the fiber.
    Type: Grant
    Filed: December 21, 2023
    Date of Patent: May 27, 2025
    Assignee: MOCHIDA PHARMACEUTICAL CO., LTD.
    Inventors: Shoji Furusako, Tsutomu Satoh, Tomohiro Narumi, Shingo Sato
  • Publication number: 20250089306
    Abstract: A semiconductor device includes an element region and a termination region. The semiconductor device includes a first electrode, a first semiconductor region, a second semiconductor region, a plurality of third semiconductor regions, a plurality of fourth semiconductor regions, a fifth semiconductor region, a sixth semiconductor region, a gate electrode, and a second electrode. The plurality of third semiconductor regions is arranged in a second direction. A pitch in the termination region of the plurality of third semiconductor regions increases away from the element region in the second direction. The plurality of fourth semiconductor regions is separated from the third semiconductor regions in the second direction. The plurality of fourth semiconductor regions is alternately arranged with the plurality of third semiconductor regions in the second direction.
    Type: Application
    Filed: March 12, 2024
    Publication date: March 13, 2025
    Inventor: Shingo SATO
  • Patent number: 12224345
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second electrode, a gate electrode, second semiconductor regions of a second conductivity type, third semiconductor regions of the first conductivity type, and a third electrode. The second electrode is provided in a plurality in second and third directions. Each second electrode opposes a portion of the first semiconductor region in the second and third directions with an insulating layer interposed. The gate electrode is provided around each second electrode. The first semiconductor region includes first regions provided respectively around the second electrodes and the second region provided around the first regions in the second and third directions. Impurity concentration of the first conductivity type in each of the first regions is higher than impurity concentration of the first conductivity type in the second region.
    Type: Grant
    Filed: October 18, 2023
    Date of Patent: February 11, 2025
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Kentaro Ichinoseki, Tatsuya Nishiwaki, Shingo Sato
  • Publication number: 20240369145
    Abstract: A housing has a housing main body and an outlet port. The housing main body includes a cylindrical housing inner wall that defines an internal space therein. The outlet port fluidly connects the internal space and an outside of the housing main body to each other. The valve has a valve body rotatable about an rotation axis along a rotation axis of the cylindrical housing inner wall. The valve is configured to selectively open and close the outlet port depending on a rotation position of the valve. The housing inner wall is formed such that a distance between the housing inner wall and the axis of the housing inner wall varies in a circumferential direction.
    Type: Application
    Filed: July 18, 2024
    Publication date: November 7, 2024
    Inventors: Shingo SATO, Yuto SATO, Masato ICHIKAWA, Akihiko GOTO, Tadashi IKEMOTO, Ryo NOMURA, Ryuki TSUJI, Takahito SUZUKI, Shogo KANZAKI
  • Publication number: 20240297220
    Abstract: A semiconductor device includes a semiconductor layer, first and second electrodes, a control electrode, and a connection region. The semiconductor layer includes first to third semiconductor regions. The connection region is positioned between the first electrode and the first semiconductor region. The connection region includes a compound of a first metallic element and Si, and a compound of Pt and Si. The first metallic element is at least one selected from the group consisting of Ti, V, Cr, Zr, Mo, Hf, Ta, and W. The connection region includes a first part adjacent to an n-type region of the semiconductor layer in a first direction. A peak position of a concentration distribution of the first metallic element in the first direction of the first part is between the n-type region and a peak position of a concentration distribution of Pt in the first direction of the first part.
    Type: Application
    Filed: August 22, 2023
    Publication date: September 5, 2024
    Inventors: Masatsugu NAGAI, Shingo SATO
  • Publication number: 20240297213
    Abstract: A semiconductor device includes first and second electrodes, first to sixth semiconductor regions, and a gate electrode. The first semiconductor region is located on the first electrode. The second semiconductor region is located on the first semiconductor region. The second semiconductor region includes a first part and a second part. The second part is located on a portion of the first part. The third semiconductor region is located on an other portion of the first part. The fourth semiconductor region separated from the third semiconductor region with the second part interposed. The fifth semiconductor region is located on the third semiconductor region. The sixth semiconductor region is located on the fifth semiconductor region. The gate electrode faces the portion of the fifth semiconductor region via a gate insulating layer. The second electrode is located on the fifth and sixth semiconductor regions.
    Type: Application
    Filed: September 1, 2023
    Publication date: September 5, 2024
    Inventor: Shingo SATO
  • Patent number: 12078253
    Abstract: A housing has a housing main body and an outlet port. The housing main body includes a cylindrical housing inner wall that defines an internal space therein. The outlet port fluidly connects the internal space and an outside of the housing main body to each other. The valve has a valve body rotatable about an rotation axis along a rotation axis of the cylindrical housing inner wall. The valve is configured to selectively open and close the outlet port depending on a rotation position of the valve. The housing inner wall is formed such that a distance between the housing inner wall and the axis of the housing inner wall varies in a circumferential direction.
    Type: Grant
    Filed: August 31, 2023
    Date of Patent: September 3, 2024
    Assignee: DENSO CORPORATION
    Inventors: Shingo Sato, Yuto Sato, Masato Ichikawa, Akihiko Goto, Tadashi Ikemoto, Ryo Nomura, Ryuki Tsuji, Takahito Suzuki, Shogo Kanzaki
  • Publication number: 20240252699
    Abstract: An ultraviolet light emission device includes: an excimer lamp having an elongated shape and having a light emission surface that emits ultraviolet light toward an object for irradiation; a light intensity sensor that is disposed around the excimer lamp and detects ultraviolet light; and a first reflection member disposed around the excimer lamp and facing a part of the light emission surface in a longitudinal direction, wherein ultraviolet light emitted from the light emission surface is reflected by the first reflection member and enters the light intensity sensor.
    Type: Application
    Filed: January 24, 2024
    Publication date: August 1, 2024
    Applicant: Ushio Denki Kabushiki Kaisha
    Inventors: Keita YOSHIHARA, Shingo SATO, Hajime ISHIHARA
  • Publication number: 20240174959
    Abstract: There has been demand for an additional method for producing antibodies. The present invention provides: a polymer-coated crosslinked alginate gel fiber in which a core layer containing a crosslinked alginate gel and either antibody-producing cells (e.g., antibody-producing CHO cells) or bioactive-substance-producing cells (e.g., MIN6 cells derived from pancreatic ? cells) is coated with a cationic polymer; and a method for producing antibodies, a bioactive substance, etc., using the fiber.
    Type: Application
    Filed: December 21, 2023
    Publication date: May 30, 2024
    Applicant: MOCHIDA PHARMACEUTICAL CO., LTD.
    Inventors: Shoji FURUSAKO, Tsutomu SATOH, Tomohiro NARUMI, Shingo SATO
  • Publication number: 20240132854
    Abstract: There has been demand for an additional method for producing antibodies. The present invention provides: a polymer-coated crosslinked alginate gel fiber in which a core layer containing a crosslinked alginate gel and either antibody-producing cells (e.g., antibody-producing CHO cells) or bioactive-substance-producing cells (e.g., MIN6 cells derived from pancreatic ? cells) is coated with a cationic polymer; and a method for producing antibodies, a bioactive substance, etc., using the fiber.
    Type: Application
    Filed: December 27, 2021
    Publication date: April 25, 2024
    Applicant: MOCHIDA PHARMACEUTICAL CO., LTD.
    Inventors: Shoji FURUSAKO, Naoto TSUDA, Tsutomu SATOH, Tomohiro NARUMI, Shingo SATO
  • Patent number: 11959147
    Abstract: A top-blowing lance nozzle is configured to freely switch an adequate expansion condition so as to control an oxygen-blowing amount and a jetting velocity independently of each other without requiring a plurality of lance nozzles or a mechanically movable part. A lance nozzle is configured to blow refining oxygen to molten iron charged in a reaction vessel while a gas is blown from a top-blowing lance to the molten iron. One or more blowing holes for blowing a working gas are on an inner wall side surface of the nozzle, at a site where the lance nozzle has a minimum cross-sectional area in a nozzle axis direction or at a neighboring site of the site.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: April 16, 2024
    Assignee: JFE STEEL CORPORATION
    Inventors: Yumi Murakami, Nobuhiko Oda, Yusuke Fujii, Goro Okuyama, Shota Amano, Shinji Koseki, Shingo Sato, Yukio Takahashi, Ryo Kawabata, Naoki Kikuchi, Atsuo Yuasa
  • Publication number: 20240097023
    Abstract: A semiconductor device includes: a semiconductor part including a first semiconductor layer and a second semiconductor layer in contact with the first semiconductor layer; a first electrode electrically connected to the first semiconductor layer on a front surface side or a back surface side of the semiconductor part; a second electrode electrically connected to the second semiconductor layer on the front surface side of the semiconductor part; a gate electrode; an interlayer insulating film electrically insulating the gate electrode and the second electrode on the front surface side of the semiconductor part; and a third semiconductor layer having: a first region in contact with the second semiconductor layer and the second electrode on the front surface side of the semiconductor part; and a second region provided between the interlayer insulating film and the second electrode in a second direction perpendicular to a first direction.
    Type: Application
    Filed: February 21, 2023
    Publication date: March 21, 2024
    Inventors: Yuhki FUJINO, Tsuyoshi KACHI, Katsura MIYASHITA, Shingo SATO
  • Publication number: 20240072167
    Abstract: According to one embodiment, a semiconductor device includes a first electrode, a first semiconductor region of a first conductivity type, a second electrode, a gate electrode, second semiconductor regions of a second conductivity type, third semiconductor regions of the first conductivity type, and a third electrode. The second electrode is provided in a plurality in second and third directions. Each second electrode opposes a portion of the first semiconductor region in the second and third directions with an insulating layer interposed. The gate electrode is provided around each second electrode. The first semiconductor region includes first regions provided respectively around the second electrodes and the second region provided around the first regions in the second and third directions. Impurity concentration of the first conductivity type in each of the first regions is higher than impurity concentration of the first conductivity type in the second region.
    Type: Application
    Filed: October 18, 2023
    Publication date: February 29, 2024
    Inventors: Kentaro ICHINOSEKI, Tatsuya Nishiwaki, Shingo Sato