Patents by Inventor Shingo Yoshioka

Shingo Yoshioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160264813
    Abstract: The present invention is a resin composition characterized by being able to undergo elastic deformation, having little residual strain rate and exhibiting stress relaxation properties. More specifically, the present invention relates to a resin composition wherein the stress relaxation rate (R) and the residual strain rate ?, as measured in a prescribed extension-restoration test, are as follows: 20%?R?95% and 0%???3%.
    Type: Application
    Filed: March 7, 2014
    Publication date: September 15, 2016
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD
    Inventors: Tomoaki SAWADA, Takatoshi ABE, Shingo YOSHIOKA
  • Publication number: 20160157343
    Abstract: A sheet-shaped stretchable structure used as an electronics element has a stretch of not less than 10% and includes a plurality of laminated stretchable resin sheet, and at least one hollow is provided between at least one of pairs of two adjacent ones of the laminated stretchable resin sheets.
    Type: Application
    Filed: November 18, 2015
    Publication date: June 2, 2016
    Inventors: TAKATOSHI ABE, TOMOAKI SAWADA, SHINGO YOSHIOKA
  • Publication number: 20160152016
    Abstract: Provided is a structural member for electronic devices which uses a material that is flexible and has excellent restoration properties after extension and stress relaxation properties. The structural member for electronic devices has the following properties A and B: (Property A) In a case where predetermined deformation is applied, stress that applies the deformation is relaxed (reduced) with time: and (Property B) In a case where the stress that applies deformation is 0, the deformation rarely remains while a resin composition is recovered. That is, when stress is 0, residual strain substantially becomes 0 (specifically 3% or lower).
    Type: Application
    Filed: October 28, 2015
    Publication date: June 2, 2016
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Takatoshi ABE, Tomoaki SAWADA, Shingo YOSHIOKA
  • Patent number: 9351402
    Abstract: A circuit board includes an electric circuit having a wiring section and a pad section in the surface of an insulating base substrate. The electric circuit is configured such that a conductor is embedded in a circuit recess formed in the surface of the insulating base substrate, and the surface roughness of the conductor is different in the wiring section and the pad section of the electric circuit. In this case, it is preferable that the surface roughness of the conductor in the pad section is greater than the surface roughness of the conductor in the wiring section.
    Type: Grant
    Filed: November 26, 2014
    Date of Patent: May 24, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda
  • Publication number: 20160143135
    Abstract: A resin composition that becomes a cured product that exhibits force response behavior such that an area surrounded by a tensile stress-strain curve f1(x), when an amount of strain is increased from 0% to 0.3% by pulling at 999 ?m/min while plotting the amount of strain on the x axis and tensile stress on the y axis, and also surrounded by the x axis, is greater than an area surrounded by a stress-strain curve f2(x), when the amount of strain is decreased from 0.3%, and also surrounded by the x axis, and the amount of change in the amount of strain when tensile stress is 0, before and after applying tensile stress, is 0.05% or less.
    Type: Application
    Filed: January 5, 2016
    Publication date: May 19, 2016
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Hiroharu INOUE, Shingo YOSHIOKA
  • Patent number: 9332642
    Abstract: One aspect of the present invention relates to a circuit board including an insulating base substrate; and a circuit layer that is formed of a conductor and that is provided on the surface of the insulating base substrate, wherein the insulating base substrate has a smooth surface having a surface roughness Ra of 0.5 ?m or less, and the conductor is at least partially embedded in a wiring groove formed in the surface of the insulating base substrate.
    Type: Grant
    Filed: September 9, 2014
    Date of Patent: May 3, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda
  • Patent number: 9332650
    Abstract: The present invention relates to a method of producing a multilayer circuit board including: a film-forming step of forming a swellable resin film on the surface of an insulative substrate, a circuit groove-forming step of forming circuit grooves having a depth equal to or greater than the thickness of the swellable resin film on the external surface of the film, a catalyst-depositing step of depositing a plating catalyst or the precursor thereof on the surface of the circuit grooves and the surface of the swellable resin film, a film-separating step of swelling the swellable resin film with a particular liquid and then separating the swollen resin film from the insulative substrate surface, and a plating processing step of forming an electrolessly plated film only in the region where the plating catalyst or the plating catalyst formed from the plating catalyst precursor remains unseparated after separation of the film.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: May 3, 2016
    Assignee: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Publication number: 20150373838
    Abstract: The present invention relates to an electrically conductive film characterized by being able to undergo elastic deformation, having little residual strain rate and exhibiting stress relaxation properties. More specifically, the present invention relates to an electrically conductive film wherein the stress relaxation rate (R) and the residual strain rate a, as measured in a prescribed extension-restoration test, are as follows: 20%?R?95% and 0%???3%.
    Type: Application
    Filed: October 8, 2014
    Publication date: December 24, 2015
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tomoaki SAWADA, Shingo YOSHIOKA, Takatoshi ABE
  • Publication number: 20150370016
    Abstract: The present invention relates to a dry film for optical waveguides, obtained through sequential stacking of a carrier film, a plating adhesion layer, an uncured cladding layer and a cover film. Solid microparticles are dispersed in a resin composition that constitutes the plating adhesion layer.
    Type: Application
    Filed: December 3, 2013
    Publication date: December 24, 2015
    Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Junko KURIZOE, Naoyuki KONDO, Toru NAKASHIBA, Shingo YOSHIOKA, Shinji HASHIMOTO
  • Patent number: 9204530
    Abstract: The present invention relates to electronic components assembly for electrically connecting electronic components to each other, wherein a wiring formed on a surface of a first electronic component and a wiring formed on a surface of a second electronic component face each other, and are bonded to each other with an electric conductor interposed therebetween, so as to electrically connect the first electronic component and the second electronic component. The electric conductor is a resin composition containing solder or conductive filler.
    Type: Grant
    Filed: April 24, 2013
    Date of Patent: December 1, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Hiromitsu Takashita, Tsuyoshi Takeda, Yuko Konno, Hiroaki Fujiwara, Shingo Yoshioka
  • Patent number: 9175151
    Abstract: The present invention relates to a resin composition which includes a copolymer consisting of a first monomer containing a monomer unit having at least one carboxyl group and a second monomer copolymerizable with the first monomer, and also includes an ultraviolet absorber. The resin composition used is a resin composition for which, when ?1 represents an absorbance coefficient per unit weight of a resin film 2 in a solution prepared by dissolving, in a solvent, the resin film 2 formed by application of the resin composition as a liquid, ?1 at a light wavelength at which the resin film 2 is to be irradiated is at least 0.01 (L/(g·cm)).
    Type: Grant
    Filed: September 25, 2014
    Date of Patent: November 3, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Yuko Konno, Hiromitsu Takashita, Tsuyoshi Takeda, Hiroaki Fujiwara, Shingo Yoshioka
  • Publication number: 20150271924
    Abstract: A wiring method is provided in which an insulating layer is formed on a surface of a semiconductor device 1 of which a plurality of connecting terminals are exposed, a resin film is formed on a surface of the insulating layer, a groove of a depth equal to or exceeding a thickness of the resin film is formed from a surface side of the resin film so that the groove passes in a vicinity of connecting terminals that are to be connected, and furthermore communicating holes which reach the connecting terminals to be connected from this portion that groove passes in the vicinity thereof are formed.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Inventors: Shingo YOSHIOKA, Hiroaki FUJIWARA, Hiromitsu TAKASHITA, Tsuyoshi TAKEDA, Yuko KONNO
  • Patent number: 9082825
    Abstract: One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching the surfaces of electrodes of the semiconductor element and a circuit groove having a desired shape and a desired depth, a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion, a film-separating step of separating the resin film from the covering insulating layer, and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated.
    Type: Grant
    Filed: October 18, 2012
    Date of Patent: July 14, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Hiromitsu Takashita, Tsuyoshi Takeda, Keiko Kashihara, Hiroaki Fujiwara, Shingo Yoshioka
  • Patent number: 9082438
    Abstract: One aspect of the present invention is a three-dimensional structure that has a concave-convex form including a gutter for wiring having at least partially a width of 20 ?m or less, wherein at least a part of a wiring conductor is embedded in the gutter for wiring, and a wiring that extends in such a manner as to creep along the concave-convex form is provided.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: July 14, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda
  • Patent number: 9082635
    Abstract: A wiring method is provided in which an insulating layer is formed on a surface of a semiconductor device 1 of which a plurality of connecting terminals are exposed, a resin film is formed on a surface of the insulating layer, a groove of a depth equal to or exceeding a thickness of the resin film is formed from a surface side of the resin film so that the groove passes in a vicinity of connecting terminals that are to be connected, and furthermore communicating holes which reach the connecting terminals to be connected from this portion that groove passes in the vicinity thereof are formed.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: July 14, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda, Yuko Konno
  • Patent number: 9070393
    Abstract: One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: June 30, 2015
    Assignee: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda
  • Publication number: 20150156873
    Abstract: A circuit board includes an electric circuit having a wiring section and a pad section in the surface of an insulating base substrate. The electric circuit is configured such that a conductor is embedded in a circuit recess formed in the surface of the insulating base substrate, and the surface roughness of the conductor is different in the wiring section and the pad section of the electric circuit. In this case, it is preferable that the surface roughness of the conductor in the pad section is greater than the surface roughness of the conductor in the wiring section.
    Type: Application
    Filed: November 26, 2014
    Publication date: June 4, 2015
    Inventors: Shingo YOSHIOKA, Hiroaki FUJIWARA, Hiromitsu TAKASHITA, Tsuyoshi TAKEDA
  • Publication number: 20150035202
    Abstract: The present invention relates to a manufacturing method of a molded article, including: a molded article forming step of forming a molded article by curing a resin composition on a main surface, on the side of a bendable first supporting medium, of a laminated supporting medium obtained by laminating the first supporting medium and a second supporting medium that is harder than the first supporting medium; a second-supporting medium peeling step of peeling the second supporting medium from the first supporting medium after the molded article forming step; and a first-supporting medium peeling step of peeling the first supporting medium from the molded article while bending the first supporting medium after the second-supporting medium peeling step. The shape of the first supporting medium can be maintained at a curing temperature at which the resin composition is cured in the molded article forming step.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 5, 2015
    Inventors: Tsuyoshi TAKEDA, Hiromitsu TAKASHITA, Keiko KASHIHARA, Shingo YOSHIOKA
  • Publication number: 20150037589
    Abstract: The present invention relates to a resin composition that becomes a cured product that exhibits force response behavior such that an area surrounded by a tensile stress-strain curve f1(x), when an amount of strain is increased from 0% to 0.3% by pulling at 999 ?m/min while plotting the amount of strain on the x axis and tensile stress on the y axis, and also surrounded by the x axis, is greater than an area surrounded by a stress-strain curve f2(x), when the amount of strain is decreased from 0.3%, and also surrounded by the x axis, and the amount of change in the amount of strain when tensile stress is 0, before and after applying tensile stress, is 0.05% or less.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 5, 2015
    Inventors: Hiroharu INOUE, Shingo YOSHIOKA
  • Publication number: 20150034366
    Abstract: One aspect of the present invention relates to a circuit board including an insulating base substrate; and a circuit layer that is formed of a conductor and that is provided on the surface of the insulating base substrate, wherein the insulating base substrate has a smooth surface having a surface roughness Ra of 0.5 ?m or less, and the conductor is at least partially embedded in a wiring groove formed in the surface of the insulating base substrate.
    Type: Application
    Filed: September 9, 2014
    Publication date: February 5, 2015
    Inventors: Shingo YOSHIOKA, Hiroaki FUJIWARA, Hiromitsu TAKASHITA, Tsuyoshi TAKEDA