Patents by Inventor Shingo Yoshioka

Shingo Yoshioka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150008379
    Abstract: The present invention relates to a resin composition which includes a copolymer consisting of a first monomer containing a monomer unit having at least one carboxyl group and a second monomer copolymerizable with the first monomer, and also includes an ultraviolet absorber. The resin composition used is a resin composition for which, when ?1 represents an absorbance coefficient per unit weight of a resin film 2 in a solution prepared by dissolving, in a solvent, the resin film 2 formed by application of the resin composition as a liquid, ?1 at a light wavelength at which the resin film 2 is to be irradiated is at least 0.01 (L/(g·cm)).
    Type: Application
    Filed: September 25, 2014
    Publication date: January 8, 2015
    Inventors: Yuko KONNO, Hiromitsu TAKASHITA, Tsuyoshi TAKEDA, Hiroaki FUJIWARA, Shingo YOSHIOKA
  • Patent number: 8929092
    Abstract: A circuit board includes an electric circuit having a wiring section and a pad section in the surface of an insulating base substrate. The electric circuit is configured such that a conductor is embedded in a circuit recess formed in the surface of the insulating base substrate, and the surface roughness of the conductor is different in the wiring section and the pad section of the electric circuit. In this case, it is preferable that the surface roughness of the conductor in the pad section is greater than the surface roughness of the conductor in the wiring section.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: January 6, 2015
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda
  • Patent number: 8901728
    Abstract: A three-dimensional structure in which a wiring and a pad part are provided on a surface is provided. A recessed gutter for wiring and a hole for the pad part having a depth that is greater than a thickness of the recessed gutter for wiring are provided on the surface of the three-dimensional structure. The hole for the pad part is provided in succession with the recessed gutter for wiring. At least a part of a wiring conductor is embedded in the recessed gutter for wiring and in the hole for the pad part.
    Type: Grant
    Filed: December 4, 2013
    Date of Patent: December 2, 2014
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Patent number: 8877843
    Abstract: The present invention relates to a resin composition which includes a copolymer consisting of a first monomer containing a monomer unit having at least one carboxyl group and a second monomer copolymerizable with the first monomer, and also includes an ultraviolet absorber. The resin composition used is a resin composition for which, when ?1 represents an absorbance coefficient per unit weight of a resin film 2 in a solution prepared by dissolving, in a solvent, the resin film 2 formed by application of the resin composition as a liquid, ?1 at a light wavelength at which the resin film 2 is to be irradiated is at least 0.01 (L/(g·cm)).
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: November 4, 2014
    Assignee: Panasonic Corporation
    Inventors: Yuko Konno, Hiromitsu Takashita, Tsuyoshi Takeda, Hiroaki Fujiwara, Shingo Yoshioka
  • Publication number: 20140191406
    Abstract: One aspect of the present invention resides in a manufacturing method for a semiconductor package, including a covering step of forming a covering insulating layer that covers the surface of a semiconductor element, a film-forming step of forming a resin film on the surface of the covering insulating layer, a circuit pattern-forming step of forming a circuit pattern portion including recesses reaching the surfaces of electrodes of the semiconductor element and a circuit groove having a desired shape and a desired depth, a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on the surface of the circuit pattern portion, a film-separating step of separating the resin film from the covering insulating layer, and a plating processing step of forming a circuit electrically connected to the electrodes, by applying electroless plating to the covering insulating layer, from which the resin film is separated.
    Type: Application
    Filed: October 18, 2012
    Publication date: July 10, 2014
    Applicant: Panasonic Corporation
    Inventors: Hiromitsu Takashita, Tsuyoshi Takeda, Keiko Kashihara, Hiroaki Fujiwara, Shingo Yoshioka
  • Publication number: 20140182887
    Abstract: One aspect of the present invention is a three-dimensional structure that has a concave-convex form including a gutter for wiring having at least partially a width of 20 ?m or less, wherein at least a part of a wiring conductor is embedded in the gutter for wiring, and a wiring that extends in such a manner as to creep along the concave-convex form is provided.
    Type: Application
    Filed: March 4, 2014
    Publication date: July 3, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Shingo YOSHIOKA, Hiroaki FUJIWARA, Hiromitsu TAKASHITA, Tsuyoshi TAKEDA
  • Publication number: 20140183751
    Abstract: One aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, the three-dimensional structure having an insulating resin layer that contains a filler formed from at least one element selected from typical non-metal elements and typical metal elements, wherein a recessed gutter for wiring is formed on a surface of the insulating resin layer, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.
    Type: Application
    Filed: March 4, 2014
    Publication date: July 3, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Shingo YOSHIOKA, Hiroaki FUJIWARA, Hiromitsu TAKASHITA, Tsuyoshi TAKEDA
  • Patent number: 8759148
    Abstract: A method of mounting a semiconductor chip includes: forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; depositing a plating catalyst on a surface of the wiring gutter; removing the resin coating; and forming an electroless plating coating only at a site where the plating catalyst remains.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: June 24, 2014
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Patent number: 8698003
    Abstract: One aspect of the present invention resides in a method of producing a circuit board, including a film-forming step of forming a resin film on a surface of an insulative substrate; a circuit pattern-forming step of forming a circuit pattern portion by forming a recessed portion having a depth equal to or greater than a thickness of the resin film, with an outer surface of the resin film serving as a reference; a catalyst-depositing step of depositing a plating catalyst or a precursor thereof on a surface of the circuit pattern portion and a surface of the resin film; a film-separating step of removing the resin film from the insulative substrate; and a plating step of forming an electroless plating film only in a region where the plating catalyst or the precursor thereof remains after the resin film is separated.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: April 15, 2014
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Publication number: 20140097004
    Abstract: A three-dimensional structure in which a wiring is provided on a surface is provided. At least a part of the surface of the three-dimensional structure includes an insulating layer containing filler. A recessed gutter for wiring is provided on the surface of the three-dimensional structure, and at least a part of a wiring conductor is embedded in the recessed gutter for wiring.
    Type: Application
    Filed: December 4, 2013
    Publication date: April 10, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Shingo YOSHIOKA, Hiroaki FUJIWARA
  • Publication number: 20140090876
    Abstract: A three-dimensional structure in which a wiring and a pad part are provided on a surface is provided. A recessed gutter for wiring and a hole for the pad part having a depth that is greater than a thickness of the recessed gutter for wiring are provided on the surface of the three-dimensional structure. The hole for the pad part is provided in succession with the recessed gutter for wiring. At least a part of a wiring conductor is embedded in the recessed gutter for wiring and in the hole for the pad part.
    Type: Application
    Filed: December 4, 2013
    Publication date: April 3, 2014
    Applicant: PANASONIC CORPORATION
    Inventors: Shingo YOSHIOKA, Hiroaki FUJIWARA
  • Publication number: 20130337188
    Abstract: The present invention relates to a resin composition which includes a copolymer consisting of a first monomer containing a monomer unit having at least one carboxyl group and a second monomer copolymerizable with the first monomer, and also includes an ultraviolet absorber. The resin composition used is a resin composition for which, when ?1 represents an absorbance coefficient per unit weight of a resin film 2 in a solution prepared by dissolving, in a solvent, the resin film 2 formed by application of the resin composition as a liquid, ?1 at a light wavelength at which the resin film 2 is to be irradiated is at least 0.01 (L/(g·cm)).
    Type: Application
    Filed: November 28, 2011
    Publication date: December 19, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Yuko Konno, Hiromitsu Takashita, Tsuyoshi Takeda, Hiroaki Fujiwara, Shingo Yoshioka
  • Publication number: 20130319735
    Abstract: A metal-clad laminate of the present invention comprises an insulating layer, and a metal layer that is present at least on one surface side of the insulating layer. The insulating layer is a laminate of at least three layers: a center layer, a first resin layer that is present on one surface side of the center layer, and a second resin layer that is present on the other surface side of the center layer. The center layer, the first resin layer and the second resin layer each contain a cured product of a respective resin composition. The elastic modulus of the cured product of the resin composition contained in the center layer is lower than the elastic moduli of both the cured product of the resin composition contained in the first resin layer and the cured product of the resin composition contained in the second resin layer.
    Type: Application
    Filed: February 15, 2012
    Publication date: December 5, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Hiroharu Inoue, Shingo Yoshioka, Koji Kishino, Takatoshi Abe
  • Publication number: 20130265729
    Abstract: The present invention relates to electronic components assembly for electrically connecting electronic components to each other, wherein a wiring formed on a surface of a first electronic component and a wiring formed on a surface of a second electronic component face each other, and are bonded to each other with an electric conductor interposed therebetween, so as to electrically connect the first electronic component and the second electronic component. The electric conductor is a resin composition containing solder or conductive filler.
    Type: Application
    Filed: April 24, 2013
    Publication date: October 10, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Hiromitsu TAKASHITA, Tsuyoshi TAKEDA, Yuko KONNO, Hiroaki FUJIWARA, Shingo YOSHIOKA
  • Patent number: 8482137
    Abstract: One aspect of the present invention is a method of mounting a semiconductor chip having: a step of forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; a step of forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; a step of depositing a plating catalyst on a surface of the wiring gutter; a step of removing the resin coating; and a step of forming an electroless plating coating only at a site where the plating catalyst remains.
    Type: Grant
    Filed: January 26, 2010
    Date of Patent: July 9, 2013
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara
  • Patent number: 8433183
    Abstract: A recording apparatus and a recording method that can record both moving picture data and still picture data in a form reproducible by various reproducing apparatus. The moving picture data is compressed by an MPEG system by an MPEG encoder, formed into data for recording corresponding to a predetermined recording format by a format forming unit, and then recorded on a DVD. The still picture data is compressed by a JPEG system by a JPEG encoder, and recorded on the DVD separately from the moving picture data. In predetermined timing, the still picture data compressed by the JPEG system and recorded on the DVD is read, the still picture data is converted into I-pictures of the MPEG system by a format converting unit, and then the I-pictures of the MPEG system are recorded onto the DVD in the predetermined format via the format forming unit.
    Type: Grant
    Filed: October 29, 2003
    Date of Patent: April 30, 2013
    Assignee: Sony Corporation
    Inventors: Yasuhiro Hidaka, Masaaki Kojima, Shingo Yoshioka, Hidehiko Okumura, Kaname Ogawa, Hiroki Shiina
  • Publication number: 20130056247
    Abstract: A wiring method is provided in which an insulating layer is formed on a surface of a semiconductor device 1 of which a plurality of connecting terminals are exposed, a resin film is formed on a surface of the insulating layer, a groove of a depth equal to or exceeding a thickness of the resin film is formed from a surface side of the resin film so that the groove passes in a vicinity of connecting terminals that are to be connected, and furthermore communicating holes which reach the connecting terminals to be connected from this portion that groove passes in the vicinity thereof are formed.
    Type: Application
    Filed: May 11, 2011
    Publication date: March 7, 2013
    Applicant: PANASONIC CORPORATION
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara, Hiromitsu Takashita, Tsuyoshi Takeda, Yuko Konno
  • Publication number: 20120292083
    Abstract: The present invention relates to a method of producing a circuit board, comprising: a film-forming step of forming a resin film on the surface of an insulative substrate; a circuit groove-forming step of forming circuit grooves having a depth equal to or greater than the thickness of the resin film on the external surface of the resin film; a catalyst-depositing step of depositing a plating catalyst or the precursor thereof on the surface of the circuit grooves on the insulative substrate and the surface of the resin film; a film-removing step of removing the resin film; and a plating processing step of electroless-plating the insulative substrate after removal of the resin film, wherein a partial reinforcing structure is formed in a region of the circuit groove in the circuit groove-forming step.
    Type: Application
    Filed: July 31, 2012
    Publication date: November 22, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Shingo YOSHIOKA, Hiroaki FUJIWARA
  • Publication number: 20120285736
    Abstract: The present invention relates to a method of producing a multilayer circuit board including: a film-forming step of forming a swellable resin film on the surface of an insulative substrate, a circuit groove-forming step of forming circuit grooves having a depth equal to or greater than the thickness of the swellable resin film on the external surface of the film, a catalyst-depositing step of depositing a plating catalyst or the precursor thereof on the surface of the circuit grooves and the surface of the swellable resin film, a film-separating step of swelling the swellable resin film with a particular liquid and then separating the swollen resin film from the insulative substrate surface, and a plating processing step of forming an electrolessly plated film only in the region where the plating catalyst or the plating catalyst formed from the plating catalyst precursor remains unseparated after separation of the film.
    Type: Application
    Filed: June 12, 2012
    Publication date: November 15, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Shingo YOSHIOKA, Hiroaki FUJIWARA
  • Patent number: 8272126
    Abstract: An object of an aspect of the present invention is to provide a method of producing a circuit board that allows highly accurate preservation of the circuit profile and gives a circuit having a desired depth in preparation of a fine circuit by additive process.
    Type: Grant
    Filed: April 29, 2009
    Date of Patent: September 25, 2012
    Assignee: Panasonic Corporation
    Inventors: Shingo Yoshioka, Hiroaki Fujiwara