Abstract: A transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. The active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.

Abstract: A display device includes a data conductive layer including a first power line, a passivation layer with a first opening exposing the first power line, a via layer with a second opening partially overlapping the first opening, a pixel electrode on the via layer, a connection electrode in the first and second openings, a pixel-defining film with an opening overlapping the second opening, a light-emitting layer on the pixel-defining film, the pixel electrode and the connection electrode, and a common electrode connected to the first power line. The data conductive layer includes a data base layer, a data main metal layer, and a data capping layer, the first power line includes a wire connection structure, in which the data main metal layer is recessed from sides of the data capping layer, and the common electrode is connected to the data main metal layer in the wire connection structure.

Abstract: A display device includes a substrate, an emission layer disposed on the substrate, and a plurality of signal lines disposed on the substrate, electrically connected to the emission layer, and including a first signal line. The first signal line includes a first layer including a refractory metal, a second layer disposed on the first layer and including a low-resistance metal, a third layer disposed on the second layer and including a first metal oxide, and a fourth layer disposed on the third layer and including a second metal oxide, and the first metal oxide of the third layer includes the low-resistance metal of the second layer.

Abstract: An organic light emitting display device includes a substrate, a buffer layer, an active layer, a gate insulation layer, a protective insulating layer, a gate electrode, an insulating interlayer, source and drain electrodes, and a sub-pixel structure. The buffer layer is disposed on the substrate. The active layer is disposed on the buffer layer, and has a source region, a drain region, and a channel region. The gate insulation layer is disposed in the channel region on the active layer. The protective insulating layer is disposed on the buffer layer, the source and drain regions of the active layer, and the gate insulation layer. The gate electrode is disposed in the channel region on the protective insulating layer. The insulating interlayer is disposed on the gate electrode. The source and drain electrodes are disposed on the insulating interlayer.

Abstract: A display device includes a substrate, a first and second bank patterns disposed on a substrate, a gate insulating layer overlapping the first bank pattern, a first transistor including a first and second electrodes disposed on the substrate with the first bank pattern interposed therebetween in a thickness direction, a first semiconductor pattern connected to the first electrode and the second electrode and disposed on a side surface of the first bank pattern, and a first gate electrode disposed to correspond to the first semiconductor pattern with the first semiconductor pattern and the gate insulating layer interposed therebetween, a light emitting element connected to the first transistor and having a first end part and a second end part, a first pixel electrode that contacts the first end part of the light emitting element, and a second pixel electrode that contacts the second end part of the light emitting element.

Abstract: A display device comprises a repair circuit, and a repair circuit connection pattern extending across a pixel and the repair circuit. Each of a first and second subpixels comprises a light emitting element, a first transistor connected thereto, and a second transistor connected to a gate electrode of the first transistor. The repair circuit comprises first and second repair transistors connected to a gate electrode of the first repair transistor. A first source/drain electrode of the first transistor of each of the first and second subpixels is connected to the power line, a second source/drain electrode of the first transistor of each of the first and second subpixels overlaps the repair circuit connection pattern. A first source/drain electrode of the first repair transistor is connected to the power line, and a second source/drain electrode of the first repair transistor overlaps the first repair circuit connection pattern.

Abstract: An organic light emitting display device includes a substrate, a buffer layer, an active layer, a gate insulation layer, a protective insulating layer, a gate electrode, an insulating interlayer, source and drain electrodes, and a sub-pixel structure. The buffer layer is disposed on the substrate. The active layer is disposed on the buffer layer, and has a source region, a drain region, and a channel region. The gate insulation layer is disposed in the channel region on the active layer. The protective insulating layer is disposed on the buffer layer, the source and drain regions of the active layer, and the gate insulation layer. The gate electrode is disposed in the channel region on the protective insulating layer. The insulating interlayer is disposed on the gate electrode. The source and drain electrodes are disposed on the insulating interlayer.

Abstract: A display device includes a substrate which includes a display area and a non-display area, a transistor disposed in the display area, a pad disposed in the non-display area, and an insulating layer which is disposed on the transistor and defines an opening which overlaps the pad in a plan view. The pad includes a main layer, a first auxiliary layer on the main layer, and a second auxiliary layer on the first auxiliary layer, and the second auxiliary layer defines the opening.

Abstract: An organic light emitting display device includes a substrate, a buffer layer, an active layer, a gate insulation layer, a protective insulating layer, a gate electrode, an insulating interlayer, source and drain electrodes, and a sub-pixel structure. The buffer layer is disposed on the substrate. The active layer is disposed on the buffer layer, and has a source region, a drain region, and a channel region. The gate insulation layer is disposed in the channel region on the active layer. The protective insulating layer is disposed on the buffer layer, the source and drain regions of the active layer, and the gate insulation layer. The gate electrode is disposed in the channel region on the protective insulating layer. The insulating interlayer is disposed on the gate electrode. The source and drain electrodes are disposed on the insulating interlayer.

Abstract: A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.

Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.

Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.

Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.

Abstract: A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.

Abstract: An exemplary embodiment of the present disclosure provides a transistor including: a drain electrode; a first insulating member on the drain electrode and having a tilted side wall; a source electrode on the first insulating member; an active member covering the tilted side wall of the first insulating member, a side wall of the source electrode, and a side wall of the drain electrode; a second insulating member covering the source electrode and the active member; and a gate electrode on the second insulating member and overlapping the active member, wherein the active member defines a first channel region adjacent to the drain electrode and a second channel region adjacent to the source electrode, and wherein a width of the first channel region may be greater than that of the second channel region.

Abstract: A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.

Abstract: An exemplary embodiment of the present disclosure provides a transistor including: a drain electrode; a first insulating member on the drain electrode and having a tilted side wall; a source electrode on the first insulating member; an active member covering the tilted side wall of the first insulating member, a side wall of the source electrode, and a side wall of the drain electrode; a second insulating member covering the source electrode and the active member; and a gate electrode on the second insulating member and overlapping the active member, wherein the active member defines a first channel region adjacent to the drain electrode and a second channel region adjacent to the source electrode, and wherein a width of the first channel region may be greater than that of the second channel region.

Abstract: A thin film transistor array substrate includes: a base substrate; a first transistor including a first electrode on a surface of the base substrate, a spacer, on the first electrode, a second electrode on the spacer, a first active layer contacting the first electrode, the spacer and the second electrode, and a first gate electrode opposite to the first active layer with a first insulating layer interposed therebetween; a storage capacitor including a first storage electrode integrally connected to the first electrode or the second electrode, and a second storage electrode opposite to the first storage electrode with the first insulating layer interposed therebetween, where the second storage electrode is integrally connected to the first gate electrode; and a second transistor electrically connected to the storage capacitor, where the second transistor includes a second active layer extending in a direction intersecting the base substrate.

Abstract: A transistor panel includes a channel region including an oxide of a first metal, a source region and a drain region, each including the first metal, wherein the channel region is disposed between the source and drain regions, and wherein the channel region is connected to the source and drain regions, an insulation layer disposed on the channel region, an upper electrode disposed on the insulation layer, an interlayer insulation layer disposed on the upper electrode, the source region and the drain region, and a barrier layer including a first portion disposed between the interlayer insulation layer and each of the source and drain regions, wherein the first portion of the barrier layer contacts each of the source and drain regions. The upper electrode and the barrier layer each comprise a second metal.

Abstract: An organic light emitting display device includes a substrate, a buffer layer, an active layer, a gate insulation layer, a protective insulating layer, a gate electrode, an insulating interlayer, source and drain electrodes, and a sub-pixel structure. The buffer layer is disposed on the substrate. The active layer is disposed on the buffer layer, and has a source region, a drain region, and a channel region. The gate insulation layer is disposed in the channel region on the active layer. The protective insulating layer is disposed on the buffer layer, the source and drain regions of the active layer, and the gate insulation layer. The gate electrode is disposed in the channel region on the protective insulating layer. The insulating interlayer is disposed on the gate electrode. The source and drain electrodes are disposed on the insulating interlayer.