Patents by Inventor Shinichi Chikaki
Shinichi Chikaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8981563Abstract: A semiconductor device includes a first interconnect, a porous dielectric layer formed over the first interconnect, a second interconnect buried in the porous dielectric layer and electrically connected to the first interconnect, and a carbon-containing metal film that is disposed between the porous dielectric layer and the second interconnect and isolates these layers.Type: GrantFiled: October 22, 2009Date of Patent: March 17, 2015Assignees: Renesas Electronics Corporation, Ulvac, Inc.Inventors: Shinichi Chikaki, Takahiro Nakayama
-
Patent number: 8592990Abstract: A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO2 skeleton; a second porous layer that is formed immediately above the first porous layer and includes a SiO2 skeleton; a via wiring that is provided in the first porous layer; and a trench wiring that is buried in the second porous layer. The first porous layer has a pore density x1 of 40% or below and the second porous layer has a pore density x2 of (x1+5) % or above.Type: GrantFiled: July 28, 2011Date of Patent: November 26, 2013Assignees: Renesas Electronics Corporation, ULVAC, Inc.Inventors: Shinichi Chikaki, Takahiro Nakayama
-
Patent number: 8384208Abstract: A semiconductor device capable of improving a mechanical strength of a porous silica film while inhibiting a film located on a lower layer of the porous silica film from deterioration is obtained. This semiconductor device includes an organic film formed on a semiconductor substrate, an ultraviolet light permeation suppressive film, formed on a surface of the organic film, composed of a material which is difficult to be permeable by ultraviolet light, and a first porous silica film formed on a surface of the ultraviolet light permeation suppressive film.Type: GrantFiled: July 12, 2007Date of Patent: February 26, 2013Assignees: Sanyo Electric Co., Ltd., NEC Corporation, Rohn Co., Ltd.Inventors: Yoshinori Shishida, Shinichi Chikaki, Ryotaro Yagi, Kazuo Kohmura, Hirofumi Tanaka
-
Patent number: 8330276Abstract: The semiconductor device includes a first interconnect layer insulating film, first copper interconnects that are embedded in the first interconnect layer insulating film, and an interlayer insulating film that is formed on the first copper interconnects and the first interconnect layer insulating film. The semiconductor device includes a second interconnect layer insulating film that is formed on the interlayer insulating film and second copper interconnects that are embedded in the second interconnect layer insulating film. The first and second interconnect layer insulating films include first and second low dielectric constant films, respectively. The interlayer insulating film has higher mechanical strength than the first and second interconnect layer insulating films.Type: GrantFiled: July 15, 2010Date of Patent: December 11, 2012Assignee: Renesas Electronics CorporationInventors: Noriaki Oda, Shinichi Chikaki
-
Patent number: 8310056Abstract: In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure.Type: GrantFiled: May 4, 2010Date of Patent: November 13, 2012Assignee: Renesas Electronics CorporationInventors: Noriaki Oda, Shinichi Chikaki
-
Patent number: 8273410Abstract: A process for manufacturing a hydrophobized microporous film includes: forming an organic silica insulating film 2 on a substrate 1; supplying a gaseous mixture 3 composed of a silylation gas and an inert gas in an apparatus having the substrate 1 disposed therein at a temperature of the substrate 1, the substrate 1 having the organic silica insulating film 2 formed thereon, and the temperature being equal to or higher than a dew point temperature of the silylation gas and equal to or lower than a vaporizing temperature of the silylation gas; stopping the supply of the gaseous mixture 3 into the apparatus; and heating the substrate having the organic silica insulating film 2 formed thereon, so that a hydrophobizing organic silica insulating film, in which the surface of the organic silica insulating film 2 and the surfaces of the pores are hydrophobized, can be obtained with reduced increase in the specific dielectric constant.Type: GrantFiled: September 29, 2008Date of Patent: September 25, 2012Assignees: Renesas Electronics Corporation, ULVAC Inc.Inventors: Shinichi Chikaki, Takahiro Nakayama
-
Publication number: 20120025395Abstract: A semiconductor device includes: a first porous layer that is formed over a substrate and includes a SiO2 skeleton; a second porous layer that is formed immediately above the first porous layer and includes a SiO2 skeleton; a via wiring that is provided in the first porous layer; and a trench wiring that is buried in the second porous layer. The first porous layer has a pore density x1 of 40% or below and the second porous layer has a pore density x2 of (x1+5) % or above.Type: ApplicationFiled: July 28, 2011Publication date: February 2, 2012Applicants: ULVAC, INC., RENESAS ELECTRONICS CORPORATIONInventors: Shinichi CHIKAKI, Takahiro NAKAYAMA
-
Publication number: 20120003841Abstract: A method of manufacturing a semiconductor device includes: a step of forming a porous dielectric film on a substrate; a step of disposing the substrate having the porous dielectric film formed thereon inside a chamber; a step of introducing siloxane into the chamber in which the substrate is disposed and heating the substrate to a first temperature; and a step heating the substrate to which the introduced siloxane adheres to a second temperature higher than the first temperature. A pressure inside the chamber is maintained to be equal to or lower than 1 kPa. In the present embodiment, the first temperature is equal to or higher than a temperature at which the pressure inside the chamber is a saturated vapor pressure of the siloxane, and is equal to or lower than a temperature at which a polymerization between the porous dielectric film and the siloxane starts.Type: ApplicationFiled: March 18, 2010Publication date: January 5, 2012Applicant: ULVAC, INC.Inventors: Shinichi Chikaki, Takahiro Nakayama
-
Patent number: 8022497Abstract: A semiconductor device capable of preventing an interlayer dielectric film from deterioration resulting from a liquid such as a chemical solution penetrating into the interlayer dielectric film and recovering the interlayer dielectric film from deterioration with a prescribed gas is obtained. This semiconductor device comprises a first insulating film formed on a substrate and a first gas-liquid separation film, formed on at least a part of the surface of the first insulating film, composed of a material hardly permeable by a liquid and easily permeable by a gas.Type: GrantFiled: February 28, 2007Date of Patent: September 20, 2011Assignees: Sanyo Electric Co., Ltd., NEC Corporation, Rohm Co., Ltd.Inventors: Yoshinori Shishida, Shinichi Chikaki, Ryotaro Yagi
-
Publication number: 20110204519Abstract: A semiconductor device includes a first interconnect, a porous dielectric layer formed over the first interconnect, a second interconnect buried in the porous dielectric layer and electrically connected to the first interconnect, and a carbon-containing metal film that is disposed between the porous dielectric layer and the second interconnect and isolates these layers.Type: ApplicationFiled: October 22, 2009Publication date: August 25, 2011Applicants: RENESAS ELECTRONICS CORPORATION, ULVAC, INC.Inventors: Shinichi Chikaki, Takahiro Nakayama
-
Publication number: 20110092071Abstract: Provided is a method for the effective silylation treatment of a silica-based porous insulating film having a plurality of pores. The method of producing a silylated porous insulating film (204c) includes a process whereby a porous insulating film (204b) having a plurality of pores is formed, and a process wherein a silylating material vapor (210) obtained by vaporizing silylating material containing organic silane compound having a hydrophobic group and polymerization inhibitor which inhibits the auto-polymerization of the organic silane compound is caused to act upon the porous insulating film (204b).Type: ApplicationFiled: May 26, 2009Publication date: April 21, 2011Applicants: RENESAS ELECTRONICS CORPORATION, ULVAC INC.Inventors: Keizo Kinoshita, Shinichi Chikaki, Takahiro Nakayama
-
Publication number: 20110049719Abstract: The semiconductor device includes a first interconnect layer insulating film, first copper interconnects that are embedded in the first interconnect layer insulating film, and an interlayer insulating film that is formed on the first copper interconnects and the first interconnect layer insulating film. The semiconductor device includes a second interconnect layer insulating film that is formed on the interlayer insulating film and second copper interconnects that are embedded in the second interconnect layer insulating film. The first and second interconnect layer insulating films include first and second low dielectric constant films, respectively. The interlayer insulating film has higher mechanical strength than the first and second interconnect layer insulating films.Type: ApplicationFiled: July 15, 2010Publication date: March 3, 2011Inventors: Noriaki Oda, Shinichi Chikaki
-
Publication number: 20100301495Abstract: Provided is the method for manufacturing the semiconductor device including: providing a film (organic silicon polymer film) containing a silane compound and a porogen on a substrate; providing a hole (interconnect trench) in the organic silicon polymer film using a selective etching process and providing a metallic film (barrier film and copper interconnect) in the inside of the interconnect trench; and conducting a radiation with ultraviolet over the organic silicon polymer film within an atmosphere of a reducing gas while the film is heated at a temperature of not lower than a boiling point or a decomposition temperature of the porogen to obtain a microporous film.Type: ApplicationFiled: May 25, 2010Publication date: December 2, 2010Applicant: NEC ELECTRONICS CORPORATIONInventor: Shinichi CHIKAKI
-
Publication number: 20100301488Abstract: In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure.Type: ApplicationFiled: May 4, 2010Publication date: December 2, 2010Applicant: NEC Electronics CorporationInventors: Noriaki Oda, Shinichi Chikaki
-
Publication number: 20100221433Abstract: A process for manufacturing a hydrophobized microporous film includes: forming an organic silica insulating film 2 on a substrate 1; supplying a gaseous mixture 3 composed of a silylation gas and an inert gas in an apparatus having the substrate 1 disposed therein at a temperature of the substrate 1, the substrate 1 having the organic silica insulating film 2 formed thereon, and the temperature being equal to or higher than a dew point temperature of the silylation gas and equal to or lower than a vaporizing temperature of the silylation gas; stopping the supply of the gaseous mixture 3 into the apparatus; and heating the substrate having the organic silica insulating film 2 formed thereon, so that a hydrophobizing organic silica insulating film, in which the surface of the organic silica insulating film 2 and the surfaces of the pores are hydrophobized, can be obtained with reduced increase in the specific dielectric constant.Type: ApplicationFiled: September 29, 2008Publication date: September 2, 2010Applicants: NEC ELECTRONICS CORPORATION, ULVAC INC.Inventors: Shinichi Chikaki, Takahiro Nakayama
-
Patent number: 7646101Abstract: An insulating layer is formed on a semiconductor substrate, and has a through hole for via. A porous silica layer has a trench for interconnection communicating to the through hole for via, and is formed on the insulating layer in contact therewith. A conductive layer is formed in the through hole for via and in the trench for interconnection. The insulating layer is formed from a material containing carbon, hydrogen, oxygen, and silicon, and having absorption peak attributed to Si—CH3 bond in a range from at least 1260 cm?1 to at most 1280 cm?1 (around 1274 cm?1) when measured with FT-IR. Thus, a semiconductor device having a porous insulating layer in which depth of the trench for interconnection is readily controlled, a dielectric constant is low, and increase in leakage current is less likely, as well as a manufacturing method thereof can be obtained.Type: GrantFiled: March 28, 2007Date of Patent: January 12, 2010Assignees: Rohm Co., Ltd., NEC Corporation, Sanyo Electric Co., Ltd.Inventors: Ryotaro Yagi, Shinichi Chikaki, Yoshinori Shishida
-
Publication number: 20080050566Abstract: A semiconductor device capable of improving a mechanical strength of a porous silica film while inhibiting a film located on a lower layer of the porous silica film from deterioration is obtained. This semiconductor device includes an organic film formed on a semiconductor substrate, an ultraviolet light permeation suppressive film, formed on a surface of the organic film, composed of a material which is difficult to be permeable by ultraviolet light, and a first porous silica film formed on a surface of the ultraviolet light permeation suppressive film.Type: ApplicationFiled: July 12, 2007Publication date: February 28, 2008Inventors: Yoshinori Shishida, Shinichi Chikaki, Ryotaro Yagi, Kazuo Kohmura, Hirofumi Tanaka
-
Publication number: 20070269977Abstract: In a formation method of a copper damascene multilayer wiring in a semiconductor integrated circuit device, after performing an oxidation process on a surface of copper, a heating process of 300° C. to 400° C. is performed in a reducing gas atmosphere, or a plasma annealing process is performed in a reducing gas plasma atmosphere.Type: ApplicationFiled: May 16, 2007Publication date: November 22, 2007Applicants: NEC CORPORATION, ROHM CO., LTD, SANYO ELECTRONIC CO., ULVAC, INC, RENESAS TECHNOLOGY CORPInventors: Shinichi Chikaki, Ryotaro Yagi, Yoshinori Shishida, Hirofumi Tanaka, Takahiro Nakayama, Yoko Uchida
-
Publication number: 20070228528Abstract: An insulating layer is formed on a semiconductor substrate, and has a through hole for via. A porous silica layer has a trench for interconnection communicating to the through hole for via, and is formed on the insulating layer in contact therewith. A conductive layer is formed in the through hole for via and in the trench for interconnection. The insulating layer is formed from a material containing carbon, hydrogen, oxygen, and silicon, and having absorption peak attributed to Si—CH3 bond in a range from at least 1260 cm?1 to at most 1280 cm?1 (around 1274 cm?1) when measured with FT-IR. Thus, a semiconductor device having a porous insulating layer in which depth of the trench for interconnection is readily controlled, a dielectric constant is low, and increase in leakage current is less likely, as well as a manufacturing method thereof can be obtained.Type: ApplicationFiled: March 28, 2007Publication date: October 4, 2007Inventors: Ryotaro Yagi, Shinichi Chikaki, Yoshinori Shishida
-
Publication number: 20070205484Abstract: A semiconductor device capable of preventing an interlayer dielectric film from deterioration resulting from a liquid such as a chemical solution penetrating into the interlayer dielectric film and recovering the interlayer dielectric film from deterioration with a prescribed gas is obtained. This semiconductor device comprises a first insulating film formed on a substrate and a first gas-liquid separation film, formed on at least a part of the surface of the first insulating film, composed of a material hardly permeable by a liquid and easily permeable by a gas.Type: ApplicationFiled: February 28, 2007Publication date: September 6, 2007Inventors: Yoshinori Shishida, Shinichi Chikaki, Ryotaro Yagi