Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: A data storage device that performs a process of writing to a memory a plurality of measured data sets received in time series includes: a nonvolatile memory divided in a plurality of blocks to which the measured data is written; and a write control section that performs a processing including successively writing N sets of the measured data to a given block in the nonvolatile memory, and then successively writing next N sets of the measured data to another block, wherein the write control section judges whether or not the N sets of measured data lastly written to the given block of the nonvolatile memory and another N sets of measured data obtained after the N sets of measured data lastly written to the given block contain data with a value outside a predetermined range, writes new measured data to the given block such that the N sets of measured data lastly written to the given block are not overwritten when the data with a value outside the predetermined range is included, and writes new measured data to t

Abstract: A data storage device includes: a first nonvolatile memory section; a second nonvolatile memory section having a smaller memory capacity than the first nonvolatile memory section; a first write control section that performs a cyclic write control including sequentially writing received data to one-dimensionally arranged data areas in the first nonvolatile memory section from a start toward an end thereof, and again sequentially writing the received data from the start toward the end upon reaching the end; and a second write control section that performs a cyclic write control including obtaining given information for the received data as index information, linking the index information to write address information of the received data, sequentially writing the index information to one-dimensionally arranged data areas in the second nonvolatile memory section from a start toward an end thereof, and again sequentially writing the index information from the start toward the end upon reaching the end.

Abstract: A semiconductor memory device includes: a memory section; and a control section that controls writing and reading of data with respect to the memory section, wherein the memory section includes a first memory region formed from nonvolatile memory cells, each of the memory cells storing binary data corresponding to a first polarization state and a second polarization state; and the control section controls, for all of the memory cells included in the first memory region, such that, before writing data to each of the memory cells based on new data externally inputted, the memory cell is polarized in the first polarization state, and then the memory cell is further polarized in the second polarization state.

Abstract: An electronic data management system capable of preventing confusion due to transfer of electronic data, even if electronic data attached with original attribute is transferred is provided. This system includes a transfer source server and a transfer destination server connected via a network. The transfer source server retains electronic data having attribute information attached indicating that the electronic data is the original. The transfer source server duplicates the electronic data to create new electronic data and stores the same in conjunction with information indicating that the new electronic data is a duplicate and information identifying the transfer destination server to which the original has been transferred.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: In an information processing apparatus which divides a memory area into a plurality of boxes and manages data stored in each box, security information containing at least an editing condition and an output condition set for each box is stored. In transmitting data stored in a box to an external device, security information for the transmission target data is set based on the security information set in the box. When the security information set in the box is changed, security information set for the data corresponding to the box is also changed.

Abstract: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91. The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7. A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.

Abstract: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91. The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7. A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.

Abstract: A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that penetrates the first and second dielectric layers, a plug formed in the contact hole, and a barrier layer formed above the plug, and a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug. The second dielectric layer has a property that is more difficult to be polished than the plug and the first dielectric layer.

Abstract: A method of manufacturing a ferroelectric memory device includes: forming an active element on a substrate; forming an interlayer insulating layer on the substrate; forming an opening on the interlayer insulating layer and forming a contact plug inside the opening; forming a foundation layer above the substrate; and laminating, on the foundation layer, a first electrode, a ferroelectric layer, and a second electrode. In this method, the forming of the foundation layer includes: forming a first titanium layer having a thickness less than a depth of a recess; nitriding the first titanium layer into a first titanium nitride layer; forming a second titanium layer on the first titanium nitride layer so as to at least partially fill the recess remaining on the contact plug; nitriding the second titanium layer into a second titanium nitride layer, and polishing a surface of the second titanium nitride layer.

Abstract: A method for manufacturing a ferroelectric memory includes: (a) forming first and second contact sections on a first dielectric layer formed above a base substrate; (b) forming a laminated body having a lower electrode, a ferroelectric layer and an upper electrode successively laminated; (c) forming a conductive hard mask above the laminated body and etching an area of the laminated body exposed through the hard mask, to thereby form a ferroelectric capacitor above the first contact section; (d) forming above the first dielectric layer a second dielectric layer that covers the hard mask, the ferroelectric capacitor and the second contact section; (e) forming a contact hole in the second dielectric layer which exposes the second contact section; (f) providing a conductive layer in an area including the contact hole for forming a third contact section; and (g) polishing the conductive layer and the second dielectric layer until the hard mask above the ferroelectric capacitor is exposed.

Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETS by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: A showerhead used for forming a ferroelectric film includes: a first gas chamber that is charged with a first gas including at least a metal element composing the ferroelectric film; a second gas chamber that is charged with at least a second gas that reacts with the first gas; a first nozzle connected to the first gas chamber; and a second nozzle connected to the second gas chamber, wherein the first nozzle is equipped with a first discharge nozzle that discharges the first gas, the second nozzle is equipped with a second discharge nozzle that discharges the second gas, and the first discharge nozzle protrudes greater than the second discharge nozzle.

Abstract: To securely prevent hydrogen from entering a ferroelectric layer of a ferroelectric memory. A first hydrogen barrier layer 5 is formed on the lower side of ferroelectric capacitors 7. Upper surfaces and side surfaces of the ferroelectric capacitors 7 are covered by a second hydrogen barrier layer. All upper electrodes 7c of the plural ferroelectric capacitors 7 to be connected to a common plate line P are connected to one another by an upper wiring layer 91. The upper wiring layer 91 is connected to the plate line P through a lower wiring 32 provided below the ferroelectric capacitors 7. A third hydrogen barrier layer 92 is formed on the upper wiring layer 91 such that all edge sections 92a of the third hydrogen barrier layer 92 come in contact with the first hydrogen barrier layer 5.

Abstract: A ferroelectric capacitor includes: a base substrate; a first electrode provided above the base substrate; a ferroelectric layer provided above the first electrode; a conductive film provided on the ferroelectric layer; a sacrificial layer composed of dielectric material provided above the conductive film; and a second electrode provided above the sacrificial layer.

Abstract: An image processing apparatus includes a receiving unit configured to externally receive print data including information on an attribute of an image to print, a rasterizing unit configured to generate raster image data based on the print data received by the receiving unit, an attribute data generating unit configured to generate attribute data representing an attribute of an image included in the raster image data generated by the rasterizing unit based on the information on an attribute of an image to print included in the print data, and a vectorizing unit configured to vectorize at least a part of the raster image data. The vectorizing unit identifies the attribute of the image included in the raster image data based on the attribute data generated by the attribute data generating unit, and performs vectorization based on the identified attribute of the image.

Abstract: A Co silicide layer having a low resistance and a small junction leakage current is formed on the surface of the gate electrode, source and drain of MOSFETs by silicidizing a Co film deposited on a main plane of a wafer by sputtering using a high purity Co target having a Co purity of at least 99.99% and Fe and Ni contents of not greater than 10 ppm, preferably having a Co purity of 99.999%.

Abstract: A semiconductor device includes a substrate, a first electrode provided above the substrate, a ferroelectric layer provided above the first electrode, a second electrode provided above the ferroelectric layer, and a dielectric side spacer that is provided above the first electrode and on a side surface of at least the ferroelectric layer.