Abstract: A ferroelectric memory includes a substrate, an interlayer dielectric layer composed of at least one layer formed above the substrate, a plurality of ferroelectric capacitors formed above the interlayer dielectric layer, a coating layer that covers the plurality of ferroelectric capacitors, a first opening section provided between the plurality of ferroelectric capacitors, a second opening section that is connected to the first opening section and formed in the coating layer and the interlayer dielectric layer, and a conductive layer provided in one piece inside the first opening section and the second opening section.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An image processing apparatus includes a comparison unit adapted to compare a color of a first master page and a color of an edge area of an object in a variable page, and a change unit adapted to, when the color difference between the first master page and the edge area of the object is equal to or less than a predetermined threshold value, change the first master page to a second master page having a color that is not similar to the color of the object.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and’ a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: A method for manufacturing a ferroelectric memory includes: (a) forming first and second contact sections on a first dielectric layer formed above a base substrate; (b) forming a laminated body having a lower electrode, a ferroelectric layer and an upper electrode successively laminated; (c) forming a conductive hard mask above the laminated body and etching an area of the laminated body exposed through the hard mask, to thereby form a ferroelectric capacitor above the first contact section; (d) forming above the first dielectric layer a second dielectric layer that covers the hard mask, the ferroelectric capacitor and the second contact section; (e) forming a contact hole in the second dielectric layer which exposes the second contact section; (f) providing a conductive layer in an area including the contact hole for forming a third contact section; and (g) polishing the conductive layer and the second dielectric layer until the hard mask above the ferroelectric capacitor is exposed.

Abstract: The invention provides a semiconductor device and a method for manufacturing the same that are capable of improving the product performance and operational efficiency of a cross-point FeRAM, as well as increasing the area of capacitors included in the cross-point FeRAM. An upper electrode supporting layer forming mask for forming an upper electrode supporting layer can be made of a hard mask material. By making use of the upper electrode supporting layer forming mask remaining unremoved in forming and processing a lower electrode layer, prior to forming an upper electrode layer, a region where a ferroelectric capacitor is formed can be made larger than an area occupied by an intersection of the upper electrode layer and the lower electrode layer.

Abstract: A ferroelectric memory includes a base member, a first dielectric layer formed above the base member, a second dielectric layer formed above the first dielectric layer, a contact hole that penetrates the first and second dielectric layers, a plug formed in the contact hole, and a barrier layer formed above the plug, and a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug. The second dielectric layer has a property that is more difficult to be polished than the plug and the first dielectric layer.

Abstract: A ferroelectric memory includes a base member, a dielectric layer formed above the base member, a contact hole that penetrates the dielectric layer, a plug formed inside the contact hole, a barrier layer formed above the plug, and including a first portion with a portion formed in the contact hole and a second portion formed integrally with the first portion and above the dielectric layer, and a ferroelectric capacitor formed from a lower electrode, a ferroelectric layer and an upper electrode successively laminated in a region including above the plug.

Abstract: A ferroelectric memory has a plurality of adjacent first and second word lines 161 and 162 arranged in word line pairs along a row direction, and a plurality of bit lines 130 arranged along a column direction intersecting the row direction. A plurality of cell capacitors 110 are arranged in a staggered manner within a word line pair and are alternately connected to the first and second word lines 161 and 162 of the word line pair. The first and second word lines 161 and 162 within a word line pair are selected in unison, each cell capacitors is individually selectable by selecting an appropriate bit line and word line pair.

Abstract: A manufacturing method for a semiconductor device that has a first region for memory elements and a second region for elements other than memory elements on a substrate, includes forming a first interlayer dielectric film on the substrate. A first opening section, which is made to reach the substrate, is formed in the first interlayer dielectric film over the first region. A second opening section, which also reaches the substrate, is formed in the first interlayer dielectric film over the second region. A first plug electrode is formed in the first opening section and a second plug electrode is formed in the second opening section. A ferroelectric capacitor is formed on the first interlayer dielectric film and made to cover and contact the first plug electrode. A first wiring pattern covering and contacting the second plug electrode is formed on the first interlayer dielectric film.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and? a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: The invention provides a method for manufacturing a semiconductor device by which product performance and working efficiency can be improved while increasing a capacitor area of cross-point FeRAM. By using a first mask formed on a lower electrode layer forming film, a lower electrode is formed and processed and the lower electrode 2A can be exposed on a first insulating layer. By using a second mask formed on an upper electrode supporting layer forming film, a ferroelectric layer and an upper electrode supporting layer can be formed and processed and the upper electrode supporting layer can be exposed on a second insulating layer.

Abstract: An implantation step of a dopant ion for forming source and drain regions (S and D) is divided into one implantation of a dopant ion for forming a p/n junction with a well region (3), and one implantation of a dopant ion that does not influence a position of the p/n junction between the source and drain regions (S and D) and the well region with a shallow implantation depth and a large implantation amount. After conducting an activation heat treatment of the dopant, a surface of the source/drain region is made into cobalt silicide 12, so that the source/drain region (S and D) can have a low resistance, and a p/n junction leakage can be reduced.

Abstract: The invention provides a semiconductor device and a method for manufacturing the same that are capable of contributing to a further chip downsizing in the cross-point FeRAM. More particularly, a first local wiring can be formed on a first interlayer insulating layer so as to connect a drain region and part of a gate electrode in a MOS transistor and a top layer wiring. A second local wiring can be formed on a second interlayer insulating layer so as to connect a source region in the MOS transistor and a lower electrode layer in a ferroelectric capacitor, and further to connect part of a gate electrode in the MOS transistor and the top layer wiring. The MOS transistor that makes up of a peripheral circuitry using only the first and second local wiring can be formed directly under a capacitor array forming region of cross-point FeRAM.