Patents by Inventor Shinichi Horiba
Shinichi Horiba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8729642Abstract: A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region.Type: GrantFiled: October 3, 2011Date of Patent: May 20, 2014Inventors: Eiji Kitamura, Shinichi Horiba, Nobuyuki Nakamura
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Patent number: 8395232Abstract: A semiconductor device includes an antifuse element. The semiconductor device includes a first well of a first conductivity type disposed in a semiconductor substrate; a first insulating film on the first well; a first conductive film of the first conductivity type on the first insulating film; and an impurity-introduced region of the first conductivity type. The impurity-introduced region of the first conductivity type in the first well is higher in impurity concentration than the first well. The impurity-introduced region includes a first portion that faces toward the first conductive film through the first insulating film.Type: GrantFiled: July 14, 2010Date of Patent: March 12, 2013Assignee: Elpida Memory, Inc.Inventors: Shinichi Horiba, Nobuyuki Nakamura, Eiji Kitamura
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Publication number: 20120018841Abstract: A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region.Type: ApplicationFiled: October 3, 2011Publication date: January 26, 2012Applicant: ELPIDA MEMORY, INC.Inventors: Eiji KITAMURA, Shinichi HORIBA, Nobuyuki NAKAMURA
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Publication number: 20110018066Abstract: A semiconductor device includes an antifuse element. The semiconductor device includes a first well of a first conductivity type disposed in a semiconductor substrate; a first insulating film on the first well; a first conductive film of the first conductivity type on the first insulating film; and an impurity-introduced region of the first conductivity type. The impurity-introduced region of the first conductivity type in the first well is higher in impurity concentration than the first well. The impurity-introduced region includes a first portion that faces toward the first conductive film through the first insulating film.Type: ApplicationFiled: July 14, 2010Publication date: January 27, 2011Applicant: Elpida Memory, Inc.Inventors: Shinichi Horiba, Nobuyuki Nakamura, Eiji Kitamura
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Publication number: 20090189248Abstract: A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region.Type: ApplicationFiled: January 30, 2009Publication date: July 30, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Eiji KITAMURA, Shinichi HORIBA, Nobuyuki NAKAMURA
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Patent number: 6861319Abstract: There is provided a method of fabricating a gate electrode, including the steps of (a) forming a gate oxide film at a surface of a semiconductor substrate, (b) forming a multi-layered structure on the gate oxide film, the multi-layered structure including a polysilicon layer formed on the gate oxide film, a refractive metal silicide layer formed on the polysilicon layer, and a silicon nitride layer formed on the refractive metal silicide layer, (c) thermally annealing the multi-layered structure in a nitrogen atmosphere to thereby form a silicon nitride film on sidewalls of the polysilicon layer and the refractive metal silicide layer, and (d) oxidizing the semiconductor substrate and the multi-layered structure.Type: GrantFiled: February 3, 2003Date of Patent: March 1, 2005Assignee: Elpida Memory, Inc.Inventors: Akira Hoshino, Kanta Saino, Shinichi Horiba, Tsutomu Hayakawa
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Publication number: 20030173582Abstract: In a solid-state imaging device, an insulation film is used to fill a separating region that divides a charge transfer electrode in the row direction, thereby achieving flattening, after which an interlayer insulation film and a metal light-shielding film are formed.Type: ApplicationFiled: February 27, 2003Publication date: September 18, 2003Applicant: NEC Electronics Corp.Inventors: Keisuke Hatano, Shinichi Horiba
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Publication number: 20030146457Abstract: There is provided a method of fabricating a gate electrode, including the steps of (a) forming a gate oxide film at a surface of a semiconductor substrate, (b) forming a multi-layered structure on the gate oxide film, the multi-layered structure including a polysilicon layer formed on the gate oxide film, a refractive metal silicide layer formed on the polysilicon layer, and a silicon nitride layer formed on the refractive metal silicide layer, (c) thermally annealing the multi-layered structure in a nitrogen atmosphere to thereby form a silicon nitride film on sidewalls of the polysilicon layer and the refractive metal silicide layer, and (d) oxidizing the semiconductor substrate and the multi-layered structure.Type: ApplicationFiled: February 3, 2003Publication date: August 7, 2003Inventors: Akira Hoshino, Kanta Saino, Shinichi Horiba, Tsutomu Hayakawa
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Patent number: 6580105Abstract: In a solid-state imaging device, an insulation film is used to fill a separating region that divides a charge transfer electrode in the row direction, thereby achieving flattening, after which an interlayer insulation film and a metal light-shielding film are formed.Type: GrantFiled: December 22, 1999Date of Patent: June 17, 2003Assignee: NEC Electronic CorporationInventors: Keisuke Hatano, Shinichi Horiba
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Publication number: 20020130343Abstract: There is provided a semiconductor memory device including (a) a semiconductor substrate on which a circuit is formed, (b) a first interlayer insulating film formed on the semiconductor substrate, (c) a plurality of bit lines formed on the first interlayer insulating film, a contact hole being formed through the first interlayer insulating film between adjacent bit lines such that the contact hole reaches the semiconductor substrate, (d) a second interlayer insulating film formed on the first interlayer insulating film such that the second interlayer insulating film covers the bit lines therewith, (e) a first electrically conductive layer buried in the contact hole, a recess being formed through the second interlayer insulating film between adjacent bit lines such that the recess reaches the first electrically conductive layer, and (f) a second electrically conductive layer covering a bottom and an inner sidewall of the recess therewith such that the second electrically conductive layer is electrically isolateType: ApplicationFiled: May 16, 2002Publication date: September 19, 2002Applicant: NEC CORPORATIONInventor: Shinichi Horiba
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Patent number: 6429478Abstract: There is provided a semiconductor memory device including (a) a semiconductor substrate on which a circuit is formed, (b) a first interlayer insulating film formed on the semiconductor substrate, (c) a plurality of bit lines formed on the first interlayer insulating film, a contact hole being formed through the first interlayer insulating film between adjacent bit lines such that the contact hole reaches the semiconductor substrate, (d) a second interlayer insulating film formed on the first interlayer insulating film such that the second interlayer insulating film covers the bit lines therewith, (e) a first electrically conductive layer buried in the contact hole, a recess being formed through the second interlayer insulating film between adjacent bit lines such that the recess reaches the first electrically conductive layer, and (f) a second electrically conductive layer covering a bottom and an inner sidewall of the recess therewith such that the second electrically conductive layer is electrically isolateType: GrantFiled: August 24, 2000Date of Patent: August 6, 2002Assignee: NEC CorporationInventor: Shinichi Horiba
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Patent number: 6150228Abstract: A silicon nitride layer on a ground wire is used for an etching stopping layer so as to form a trench, after which a high-resistance load element is formed so as to extend the length of the resistance by the amount of the step of the trench, and by forming the high-resistance load element in two layers, the resistance length is made large.Type: GrantFiled: May 26, 1998Date of Patent: November 21, 2000Assignee: NEC CorporationInventor: Shinichi Horiba
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Patent number: 6136696Abstract: A semiconductor device that prevents any problems relating to contact resistance increase at a conductor plug and parasitic resistance increase near the conductor plug. A first patterned conductive layer is formed on a first dielectric layer, and a second patterned dielectric layer is formed on the first patterned conductive layer. A third dielectric layer is formed on the first dielectric layer to cover entirely the first patterned conductive layer and covering partially the second patterned dielectric layer. A fourth patterned dielectric layer is formed on the third dielectric layer to serve as sidewall spacers for the part the second patterned dielectric layer exposed from the third dielectric layer. A fifth dielectric layer is formed on the third dielectric layer. A contact hole is formed to penetrate through at least the fifth and third dielectric layers. A conductive plug is formed to fill the contact hole.Type: GrantFiled: March 29, 1999Date of Patent: October 24, 2000Assignee: NEC CorporationInventor: Shinichi Horiba
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Patent number: 6071785Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming a first insulating film on a semiconductor substrate, (b) forming gate electrodes on the first insulating film, the gate electrodes having a two-layered structure including a first conductive film and a second insulating film lying over the first conductive film, (c) forming a diffusion layer around the gate electrodes, (d) forming an insulating sidewall film around a sidewall of the gate electrodes, (e) covering a resultant with a third insulating film, (f) forming a contact hole between the gate electrodes in self-aligning fashion, (g) covering a resultant with a second conductive film, (h) covering a resultant with a fourth insulating film, (i) planarizing the fourth insulating film, (j) isotropically etching the planarized fourth insulating film to make a part of the second conductive film to appear, (k) covering a resultant with a third conductive film, and (l) etching the third conductive film, the fourtType: GrantFiled: November 5, 1997Date of Patent: June 6, 2000Assignee: Nec CorporationInventor: Shinichi Horiba
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Patent number: 5952724Abstract: Semiconductor elements, such as driving MOS transistors, transfer MOS transistors and the like are formed in a element region defined on the surface of a semiconductor substrate. A first interlayer insulation layer is formed on these surfaces. A grounding wiring layer is formed over substantially entire surface of the first interlayer insulation layer. Also, a silicon nitride layer and a second interlayer insulation layer are formed sequentially on the surface of the grounding wiring layer. Then, a first contact hole reaching a gate electrode of the driving MOS transistor is provided at a desired position. Then, a side wall insulation layer of silicon nitride layer is formed only on the side wall surface of the grounding wiring layer facing the contact hole.Type: GrantFiled: June 19, 1997Date of Patent: September 14, 1999Assignee: NEC CorporationInventor: Shinichi Horiba
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Patent number: 5846878Abstract: In a method of building up wiring with a protective insulator film as a mask, a precise and elaborate wiring pattern is formed. The method comprises a process of making up a conductive material film on the surface of a semiconductor substrate, a process of depositing a inorganic insulator film consisting of a semiconductor oxide film and a semiconductor nitride film in layers on the conductive material film, a process of making up an antireflection film for an irradiation light for sensitizing used in photo lithography which patterns photosensitivity resist film, a process of making up the photosensitivity resist film on the antireflection film to pattern in a predetermined shape, and a process of applying dry etching to the conductive material film and the antireflection film with the inorganic insulator film as a mask.Type: GrantFiled: February 28, 1997Date of Patent: December 8, 1998Assignee: NEC CorporationInventor: Shinichi Horiba
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Patent number: 5744866Abstract: There is provided a method of fabricating a semiconductor device, including the steps of (a) forming a first insulating film on a semiconductor substrate, (b) forming gate electrodes on the first insulating film, the gate electrodes having a two-layered structure including a first conductive film and a second insulating film lying over the first conductive film, (c) forming a diffusion layer around the gate electrodes, (d) forming an insulating sidewall film around a sidewall of the gate electrodes, (e) covering a resultant with a third insulating film, (f) forming a contact hole between the gate electrodes in self-aligning fashion, (g) covering a resultant with a second conductive film, (h) covering a resultant with a fourth insulating film, (i) planarizing the fourth insulating film, (j) isotropically etching the planarized fourth insulating film to make a part of the second conductive film to appear, (k) covering a resultant with a third conductive film, and (l) etching the third conductive film, the fourtType: GrantFiled: March 11, 1997Date of Patent: April 28, 1998Assignee: NEC CorporationInventor: Shinichi Horiba