SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
A semiconductor device comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region.
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1. Field of the Invention
The present invention relates to a semiconductor device used as an anti-fuse element and a method of manufacturing the semiconductor device.
2. Description of the Related Art
An anti-fuse element is normally electrically insulated but is electrically conductive when a voltage is applied to the element. The anti-fuse element is used in order to replace a defective portion of a semiconductor integrated circuit with a redundancy circuit.
As seen in
To allow proper operation of those of anti-fuse elements initially insulated by gate insulating film 104 which are to be connected, a high electric field is applied between gate electrode 101 and diffusion layer 105 to destroy gate insulating film 104, causing short-circuiting. Thus, gate electrode 101 can be connected to diffusion layer 105. This connection operation allows a high current to flow through the destroyed part of gate insulating film 104 to provide energy, resulting in ohmic contact.
In recent years, the gate insulating film has been thinned in connection with miniaturizing circuits to increase gate leakage current flowing between the gate electrode and the active region via the gate insulating film. In the anti-fuse element according to the related art described above, the increased gate leakage current may disperse the high current (energy) to areas other than the destroyed one when a high electric field is applied between the gate electrode and the diffusion layer. Thus, it may not be possible to obtain acceptable ohmic contact even after the dielectric has been destroyed, causing some elements to offer high resistance. To prevent this, a signal amplification circuit dedicated to the anti-fuse element is added or the circuit is changed such that anti-fuses are arranged in parallel to allow a logical OR operation to be performed. Then, even with the element offering high resistance, the circuit is prevented from operating inappropriately. However, this measure hinders a reduction in the size of chip area and also complicates circuit design and increases the number of steps required; thus this measure is not preferable.
SUMMARY OF THE INVENTIONIn one embodiment, there is provided a semiconductor device that comprises an active region formed in a semiconductor substrate and a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region. A peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region.
In this semiconductor device, the overlap region, in which the active region overlaps the gate electrode is made smaller to enable a reduction in gate leakage current and in the area that is to be destroyed. Thus, even with the thinned gate insulating film, current that flows when the gate insulating film is destroyed is inhibited from dispersing. This allows an ohmic connection to be easily made. Furthermore, the overlap region can be made smaller without the need for miniaturization based on processing. This eliminates the need to increase the number of steps required. Thus, a semiconductor device serving as a more reliable anti-fuse element can be implemented without the need to provide an additional circuit or to change a related process.
The above features and advantages of the present invention will be more apparent from the following description of certain preferred embodiments taken in conjunction with the accompanying drawings, in which:
The invention will be now described herein with reference to illustrative embodiments. Those skilled in the art will recognize that many alternative embodiments can be accomplished using the teachings of the present invention and that the invention is not limited to the embodiments illustrated for explanatory purposes.
Referring to
Gate leakage current, which is a factor reducing the reliability of the anti-fuse element, is known to be generally in proportion to gate capacity, that is, the area of overlap region 3, which is an effective gate area. According to the related art, in patterning of gate electrode 101 and active region 102 in a semiconductor device which has the same layout as that of a common MOS transistor, the area of overlap region 103 cannot be made smaller than that achieved when gate electrode 101 and active region 102 are formed so as to have minimum processing dimensions determined based on the resolution limit of lithography. However, in the semiconductor device according to the present embodiment, by positioning gate electrode 1 so as to prevent active region 2 from being divided into at least two independent regions (diffusion layers), overlap region 3, formed by gate electrode 1 and active region 2, can be made much smaller than the overlap region in the semiconductor device according to the related art. Thus, even with thinned gate insulating film 4, the gate leakage current can be significantly reduced, enabling the reliability of the anti-fuse element to be improved.
Furthermore, gate electrode 1 and active region 2 are arranged so that the peripheral portion of gate electrode 1 overlaps the peripheral portion of active region 2. Thus, only one diffusion layer 5 is constructed. Consequently, pattern edge A corresponding to an edge portion between a planar pattern of overlap region 3 and a planar pattern of diffusion layer 5, shown by a thick line in
In the layout of the related art, the total length of pattern edge A is minimized if active region 2 is formed with minimum processing dimensions defined by the resolution limit of lithography. However, a layout such as that of the semiconductor device according to the present embodiment allows pattern edge A to be easily shortened. Furthermore, the length of pattern edge A can be made further smaller than a value twice the minimum processing dimension in active region 2, which corresponds to the minimum length in the layout of the related art.
As described above, overlap region 3 and pattern edge A in the semiconductor device according to the present embodiment can be made smaller than the overlap region and pattern edge in the semiconductor device according to the related art without the need for miniaturization based on processing. Thus, possible gate leakage current and the area to be destroyed can be reduced. Consequently, even with thinned gate insulating film 4, current that flows when gate insulating film 4 is destroyed is inhibited from being dispersed. This allows an ohmic connection to be easily made. Therefore, a semiconductor device as a more reliable anti-fuse element can be implemented.
Now, with reference to
The method of manufacturing the semiconductor device of the present embodiment includes forming the active region on the semiconductor substrate, and forming the gate electrode on the active region via the gate insulating film. The formation of the gate electrode includes forming the gate insulating film on the surface of the active region, and forming the gate electrode on the gate insulating film so that the peripheral portion of the gate electrode overlaps the peripheral portion of the active region at the position where the active region is not divided by the gate electrode, so as to form the overlap region.
First, as shown in
Now, with reference to
Subsequently, as shown in
Finally, as shown in
As described above, like the anti-fuse element of the related art, the semiconductor device, according to the present embodiment, which is used as an anti-fuse element has the same film structure as that of transistors typically used in circuits. Thus, the semiconductor device, according to the present embodiment, which is used as an anti-fuse element has the great advantage of enabling the anti-fuse characteristic to be improved without the need to change a related process or to increase the number of steps required.
Other embodiments of the semiconductor device according to the present invention will be described with reference to
In the semiconductor device according to a second embodiment shown in
Furthermore, as shown in
In a semiconductor device according to a fourth embodiment of the present invention shown in
Referring to
In each of the above-described configuration examples, instead of the layout as in the related art wherein the plain pattern of the gate electrode is positioned so as to divide the plain pattern of the active region, the device is laid out such that the peripheral portion of each of gate electrodes 1a to 1f overlaps the peripheral portion of the corresponding active regions 2a to 2f. Thus, also in this case, each of overlap regions 3a to 3f and pattern edge A can be made smaller than the overlap regions and pattern edge according to the related art. This enables a reduction in possible gate leakage current and the area to be destroyed. Consequently, possible dispersion of current to areas other than the destroyed area is inhibited, allowing the breakage to concentrate at one point. This allows an ohmic connection to be easily made, enabling the anti-fuse characteristic to be improved.
Each of the above-described configuration examples, that is, the layout including overlap region 3a to 3f at least two positions, also has the advantage of providing an element that allows a large overlap margin to be provided between patterns during manufacture, and that allows a reliable contact to be made at any position even if overlapping misalignment occurs between the patterns.
With patterns that have a minimum lithography processing dimension of at most 0.2 μm, when a rectangular pattern or a rectangular hole pattern on the photo mask (reticle) is transferred to and formed on the resist on the semiconductor substrate, rectangular corners may be rounded owing to optical characteristics. The gate electrode pattern may be laid out with such a variation taken into account in advance.
As further embodiments of the semiconductor device according to the present invention, a more effective layout will described with reference to
A semiconductor device according to an eighth embodiment of the present invention shown in a plan view in
In the present embodiment, in
Since overlap region 3g and contact plugs 18a and 28a are thus arranged, when gate insulating film 4a is destroyed to make the anti-fuse element electrically conductive, the electric field applied between gate electrode 1g and active region 2g (diffusion layer 5a) can be made to concentrate in an area at the end of gate electrode 1g. Thus, dielectric breakdown in overlap region 3g can be allowed to occur in the vicinity of an area shown by thick line C in
Alternatively, as shown in
As shown in
As described above, the present invention allows easy manufacture of a semiconductor device which improves reliability and allows a possible variation in electric resistance value to be inhibited while the anti-fuse element is electrically conductive.
It is apparent that the present invention is not limited to the above embodiments, but may be modified and changed without departing from the scope and spirit of the invention.
Claims
1. A semiconductor device comprising:
- an active region formed in a semiconductor substrate; and
- a gate electrode formed on the active region via a gate insulating film formed on a surface of the active region;
- wherein a peripheral portion of the gate electrode and a peripheral portion of the active region overlap each other at a position where the active region is not divided by the gate electrode when viewed in plan view, thus forming an overlap region.
2. The semiconductor device according to claim 1, wherein, as viewed in plan view, the active region has a rectangular shape and the overlap region is positioned along at least one side of the active region.
3. The semiconductor device according to claim 1, wherein, as viewed in plan view, the active region has a rectangular shape and the gate electrode is provided with an opening that is smaller than the active region, and the overlap region is formed by at least a part of a peripheral portion of the active region and at least a part of a peripheral portion of the opening in the gate electrode.
4. The semiconductor device according to claim 1, wherein, as viewed in plan view, the active region comprises a central rectangular portion and an extension portion extending from the central rectangular portion, and the overlap region is positioned at the distal end of the extension portion of the active region.
5. The semiconductor device according to claim 1, wherein, as viewed in plan view, the active region has a rectangular shape and the gate electrode is provided with a rectangular opening, and wherein the overlap region is formed by a corner of the active region and a side of a peripheral portion of the opening of the gate electrode.
6. The semiconductor device according to claim 1, wherein, as viewed in plan view, the active region has a rectangular shape and the gate electrode comprises a cut portion, and wherein the overlap region is formed by a corner of the active region and a side of a peripheral portion of the cut portion of the gate electrode.
7. The semiconductor device according to claim 1, wherein, as viewed in plan view, the active region comprises a notch portion and the overlap region is positioned along at least one of a plurality of sides of the notch portion of the active region.
8. The semiconductor device according to claim 1, wherein, as viewed in plan view, the overlap region is located on a straight line that joins a first contact plug to a second contact plug and that is positioned therebetween, the first contact plug being connected to the active region that forms said overlap region, the second contact plug being connected to the gate electrode that forms said overlap region.
9. The semiconductor device according to claim 8, wherein, as viewed in plan view, the gate electrode extends along the straight line.
10. The semiconductor device according to claim 1, wherein the gate electrode and the active region operates as an anti-fuse element.
11. The semiconductor device according to claim 10, wherein the anti-fuse element flows an electric current by destroying the gate insulating film at the overlap region.
12. A semiconductor device comprising:
- a semiconductor substrate; and
- an anti-fuse element disposed on the semiconductor substrate, wherein the anti-fuse element comprises:
- an active region disposed on the semiconductor substrate, having a rectangular shape;
- an isolation region for surrounding the active region; and
- a gate electrode disposed over the active region and the isolation region, wherein the active region of the anti-fuse element has four edges for defining the rectangular shape, and the gate electrode of the antifuse is located facing to a part of the active region with an intervention of a gate insulating film therebetween, and the gate electrode of the anti-fuse element is located being across at only one edge which defines a border between the active region and the isolation region.
13. The semiconductor device according to claim 12, further comprising:
- a first contact plug connected to the gate electrode of the anti-fuse element; and
- a second contact plug connected to the active region of the anti-fuse element, wherein the edge of the active region under the gate electrode of the anti-fuse element is perpendicular to a line which connects between the first contact plug and the second contact plug.
14. The semiconductor device according to claim 13, wherein the gate electrode of the anti-fuse extends over the isolation region, along to the line which connects between the first contact plug and the second contact plug.
Type: Application
Filed: Jan 30, 2009
Publication Date: Jul 30, 2009
Applicant: ELPIDA MEMORY, INC. (Tokyo)
Inventors: Eiji KITAMURA (Tokyo), Shinichi HORIBA (Tokyo), Nobuyuki NAKAMURA (Tokyo)
Application Number: 12/362,498
International Classification: H01L 23/525 (20060101);