Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11977481
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Grant
    Filed: May 2, 2023
    Date of Patent: May 7, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Kazuhiro Fukutomi, Kenichiro Yoshii, Shinichi Kanno, Shigehiro Asano
  • Patent number: 11972110
    Abstract: According to one embodiment, in response to receiving, from a host, one or more second type commands, a controller of the storage device maintains the received one or more second type commands in a memory region in the storage device without completing processing of the received one or more second type commands. In response to receiving the first type command from the host, the controller completes processing of a second type command, and transmits a command completion response for the first type command to the host as a first preceding response for the first type command. In response to completion of processing of the first type command, the controller transmits a command completion response for the first type command to the host.
    Type: Grant
    Filed: September 12, 2022
    Date of Patent: April 30, 2024
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Kensaku Yamaguchi, Takehiko Kurashige, Yuki Sasaki
  • Publication number: 20240134552
    Abstract: A storage device includes a nonvolatile semiconductor memory device including a plurality of physical blocks and a memory controller. The memory controller is configured to associate one or more physical blocks to each of a plurality of stream IDs, execute a first command containing a first stream ID received from a host, by storing write data included in the write IO in the one or more physical blocks associated with the first stream ID, and execute a second command containing a second stream ID received from the host, by selecting a first physical block that includes valid data and invalid data, transfer the valid data stored in the first physical block to a second physical block, and associate the first physical block from which the valid data has been transferred, with the second stream ID.
    Type: Application
    Filed: December 29, 2023
    Publication date: April 25, 2024
    Inventors: Daisuke HASHIMOTO, Shinichi KANNO
  • Patent number: 11966606
    Abstract: A memory system includes a controller and a flash memory including a plurality of first blocks. The controller writes a value having a first number of bits per memory cell to a plurality of second blocks, and writes a value having a second number of bits per memory cell to a plurality of third blocks among the first blocks. The second number is more than the first number. The controller writes data from a host device to the second blocks and transcribes valid data from the second blocks to the third blocks. The controller controls the number of second blocks in the first blocks according to an order of completion of the data writing to one or more third blocks and an amount of valid data stored in each of the one or more third blocks.
    Type: Grant
    Filed: March 10, 2022
    Date of Patent: April 23, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Takahiro Kurita, Shinichi Kanno
  • Publication number: 20240126433
    Abstract: According to one embodiment, a memory system includes a non-volatile semiconductor memory, a block management unit, and a transcription unit. The semiconductor memory includes a plurality of blocks to which data can be written in both the first mode and the second mode. The block management unit manages a block that stores therein no valid data as a free block. When the number of free blocks managed by the block management unit is smaller than or equal to a predetermined threshold value, the transcription unit selects one or more used blocks that stores therein valid data as transcription source blocks and transcribes valid data stored in the transcription source blocks to free blocks in the second mode.
    Type: Application
    Filed: December 26, 2023
    Publication date: April 18, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Hiroshi YAO, Shinichi KANNO, Kazuhiro FUKUTOMI
  • Patent number: 11960719
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Kioxia Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • Patent number: 11954043
    Abstract: According to one embodiment, when a read request received from a host includes a first identifier indicative of a first region, a memory system obtains a logical address from the received read request, obtains a physical address corresponding to the obtained logical address from a logical-to-physical address translation table which manages mapping between logical addresses and physical addresses of the first region, and reads data from the first region, based on the obtained physical address. When the received read request includes a second identifier indicative of a second region, the memory system obtains physical address information from the read request, and reads data from the second region, based on the obtained physical address information.
    Type: Grant
    Filed: March 8, 2022
    Date of Patent: April 9, 2024
    Assignee: Kioxia Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Publication number: 20240111416
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Applicant: Kioxia Corporation
    Inventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO
  • Patent number: 11947837
    Abstract: According to one embodiment, a memory system receives, from a host, a write request including a first identifier associated with one write destination block and storage location information indicating a location in a write buffer on a memory of the host in which first data to be written is stored. When the first data is to be written to a nonvolatile memory, the memory system obtains the first data from the write buffer by transmitting a transfer request including the storage location information to the host, transfers the first data to the nonvolatile memory, and writes the first data to the one write destination block.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: April 2, 2024
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11947422
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: April 2, 2024
    Assignee: KIOXIA CORPORATION
    Inventors: Kenichiro Yoshii, Shinichi Kanno
  • Patent number: 11941247
    Abstract: According to one embodiment, a storage device includes a non-volatile memory and a control unit that is electrically connected to the non-volatile memory and that is configured to control the non-volatile memory. The control unit is configured to manage a plurality of management areas obtained by logically partitioning storage area of the non-volatile memory, when a write request is received that includes data for which a valid term has been set, determine, based on the valid term, a first management area from among the management areas, write the data included in the write request to the determined first management area, and when the data written to the first management area is erased, collectively erase all data written in the first management area which includes the data.
    Type: Grant
    Filed: December 11, 2020
    Date of Patent: March 26, 2024
    Assignee: Kioxia Corporation
    Inventors: Takeshi Ishihara, Yohei Hasegawa, Shinichi Kanno, Kohei Okuda, Masataka Goto
  • Publication number: 20240095163
    Abstract: According to one embodiment, in response to restoration of power to a memory system, a controller in the memory system notifies a host that the memory system is ready. When an input/output command specifying a logical address belonging to a logical address range is received, the controller selects a block corresponding to the logical address range and rebuilds, based on address translation information and an update log which are stored in the selected block, the latest address translation information corresponding to the logical address range. The controller updates the rebuilt latest address translation information, based on a list of logical addresses corresponding to lost write data, stored in the selected block.
    Type: Application
    Filed: September 8, 2023
    Publication date: March 21, 2024
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Aurelien Nam Phong TRAN, Yuki SASAKI
  • Publication number: 20240086096
    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a controller. The controller manages validity of data in the non-volatile memory using a data map. The data map includes first fragment tables. Each of the first fragment tables stores first and second information. The first information indicates the validity of each data having a predetermined size written in a range of physical address in the non-volatile memory allocated to the first fragment table. The second information indicates the validity of a plurality of data having a predetermined size in each of entries. The controller selects a write destination block based on a size of write data to be written to the non-volatile memory by a write command from a host.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Yuki SASAKI, Shinichi KANNO
  • Publication number: 20240086099
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 14, 2024
    Applicant: Kioxia Corporation
    Inventors: Naoki ESAKA, Shinichi KANNO
  • Patent number: 11922028
    Abstract: According to one embodiment, when it is determined that a first storage device of a plurality of storage devices is to be removed and an additional storage device is connected to a storage controller, the storage controller writes update data portions corresponding to data portions already written to the first storage device to any storage device selected from remaining one or more storage devices of the plurality of storage devices except for the first storage device and the additional storage device. Further, the storage controller writes update data portions corresponding to data portions already written to the remaining one or more storage devices to any storage device selected from the remaining one or more storage devices and the additional storage device.
    Type: Grant
    Filed: June 7, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11923325
    Abstract: A memory chip unit includes a pad electrode including first and second portions, and a memory cell array. A prober includes a probe card and a movement mechanism. The probe card includes a probe electrode to be in contact with the pad electrode, and a memory controller electrically coupled to the probe electrode and executes reading and writing on the memory cell array. The movement mechanism executes a first operation that brings the probe electrode into contact with the first portion and does not bring the probe electrode into contact with the second portion, and a second operation that does not bring the probe electrode into contact with the first portion and brings the probe electrode into contact with the second portion.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Yasuhito Yoshimizu, Takashi Fukushima, Tatsuro Hitomi, Arata Inoue, Masayuki Miura, Shinichi Kanno, Toshio Fujisawa, Keisuke Nakatsuka, Tomoya Sanuki
  • Patent number: 11922039
    Abstract: A storage device includes a nonvolatile semiconductor memory device including a plurality of physical blocks and a memory controller. The memory controller is configured to associate one or more physical blocks to each of a plurality of stream IDs, execute a first command containing a first stream ID received from a host, by storing write data included in the write IO in the one or more physical blocks associated with the first stream ID, and execute a second command containing a second stream ID received from the host, by selecting a first physical block that includes valid data and invalid data, transfer the valid data stored in the first physical block to a second physical block, and associate the first physical block from which the valid data has been transferred, with the second stream ID.
    Type: Grant
    Filed: November 15, 2022
    Date of Patent: March 5, 2024
    Assignee: Kioxia Corporation
    Inventors: Daisuke Hashimoto, Shinichi Kanno
  • Publication number: 20240070006
    Abstract: According to one embodiment, when a code rate is less than 1, a controller encodes a plurality of pieces of write data to generate a codeword including the plurality of pieces of write data and one or more erasure recovery codes. The controller calculates a cumulative error count. The controller calculates at least one of a cumulative write amount or a cumulative read amount. The controller change the code rate such that the code rate is increased when a first value which is obtained by dividing the cumulative error count by the cumulative write amount or the cumulative read amount is less than a first threshold value, and the code rate is decreased when the first value is larger than or equal to a second threshold value.
    Type: Application
    Filed: March 8, 2023
    Publication date: February 29, 2024
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Yuki SASAKI
  • Patent number: 11914896
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory is correspond to a first mode of writing data of N bits per unit area and a second mode of writing data of M bits (M>N) per unit area. When receiving a first command issued prior to a write command to instruct writing write data to the nonvolatile memory, the controller selects one or both of the first mode and the second mode for writing the write data to the nonvolatile memory, to allow writing the write data to the nonvolatile memory to be executed in the first mode as much as possible, based on a capacity of the write data specified by the first command and a capacity of a free area of the nonvolatile memory.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Takahiro Kurita, Shinichi Kanno
  • Publication number: 20240061610
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller acquires, from a host, write data having the same first size as a data write unit of the nonvolatile memory and obtained by dividing write data associated with one write command having a first identifier indicating a first write destination block in a plurality of write destination blocks into a plurality of write data or combining write data associated with two or more write commands having the first identifier. The controller writes the acquired write data having the first size to the first write destination block by a first write operation.
    Type: Application
    Filed: November 1, 2023
    Publication date: February 22, 2024
    Applicant: KIOXIA CORPORATION
    Inventors: Shinichi KANNO, Hideki YOSHIDA, Naoki ESAKA, Hiroshi NISHIMURA