Patents by Inventor Shinichi Kanno

Shinichi Kanno has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11768632
    Abstract: According to one embodiment, a controller of a memory system executes a first write operation of writing write data into a first storage region, in response to reception of one or more write requests for specifying a first zone from a host, during a period from execution of an erase operation of the first storage region until a first time elapses. When the first time has elapsed after execution of the erase operation, in a state in which an unwritten region having a size larger than or equal to a first size remains in the first storage region, the controller does not execute the first write operation, allocates the first storage region as a nonvolatile buffer capable of temporarily storing write data to be written to each of a plurality of zones.
    Type: Grant
    Filed: December 21, 2021
    Date of Patent: September 26, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11768634
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a memory controller configured to execute a patrol process, in response to a first command set from a host device. In the patrol process, the memory controller is configured to read first data from the nonvolatile memory, and not to output the first data to the host device.
    Type: Grant
    Filed: October 24, 2022
    Date of Patent: September 26, 2023
    Assignee: Kioxia Corporation
    Inventors: Yasuhiko Kurosawa, Naomi Takeda, Masanobu Shirakawa, Yasuyuki Ushijima, Shinichi Kanno
  • Publication number: 20230297289
    Abstract: According to one embodiment, when a command executed in a nonvolatile memory is an erase/program command and when a cumulative weight value satisfies a condition that a first input is selected as an input of high priority, a memory system suspends execution of the erase/program command by transmitting a suspend command to the nonvolatile memory. The memory system repeats executing an operation of starting the execution of one read command of the first input and an operation of updating the cumulative weight by using the weight associated with the read command until read command no longer exists in the first input or until the condition that the cumulative weight is larger than the first value is not satisfied, and resumes the execution of the suspended erase/program command.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Publication number: 20230297290
    Abstract: A memory system includes a nonvolatile memory including memory dies, and a controller. The controller is configured to create a first virtual storage with a first part of the memory dies and a second virtual storage with a second part of the memory dies, and create a redundant logical domain spanning one or more memory dies corresponding to the first virtual storage and one or more memory dies corresponding to the second virtual storage. The memory controller is configured to, in response to a write command, store write data corresponding to the write command in a first region of the first virtual storage and in a second region of the second virtual storage, and return to the host a response including a first physical address of the first region and a second physical address of the second region.
    Type: Application
    Filed: August 29, 2022
    Publication date: September 21, 2023
    Inventors: Hideki YOSHIDA, Shinichi KANNO
  • Publication number: 20230297262
    Abstract: A memory system includes a volatile memory, a nonvolatile memory, and a controller. The controller is configured to set a block group of the nonvolatile memory to be in a writable state and generate in the volatile memory a list associated with the block group. The controller is configured to, with respect to a write command, add an entry to the list, which includes a first address of a host and a second address of the volatile memory, obtain the write data from the first address of the host and store the write data in the second address of the volatile memory, write the write data stored at the second address of the volatile memory into the block group, and upon the block group being fully written, set the block group to be in a non-writable state and dissociate the list from the block group.
    Type: Application
    Filed: August 29, 2022
    Publication date: September 21, 2023
    Inventors: Yuki SASAKI, Shinichi KANNO
  • Publication number: 20230297247
    Abstract: According to one embodiment, a controller of a memory system writes, in response to receiving from the host a write command specifying a logical address, data received from the host to a first write destination block. The controller manages a first list and first storage location information, the first list including a plurality of logical addresses corresponding respectively to write-uncompleted data, and the first storage location information indicating a storage location at a beginning of a write-uncompleted region in the first write destination block. In a case where a power loss has occurred without notice from the host, the controller writes the first list and the first storage location information to the nonvolatile memory using power from a capacitor.
    Type: Application
    Filed: September 9, 2022
    Publication date: September 21, 2023
    Applicant: Kioxia Corporation
    Inventors: Shinichi KANNO, Yuki SASAKI
  • Publication number: 20230297288
    Abstract: According to one embodiment, a memory system determines, for each of groups corresponding to streams, whether or not a length of write data associated with a set of write commands belonging to a same group reaches a minimum write size of a nonvolatile memory. When a length of write data associated with a set of write commands belonging to a first group corresponding to a first stream reaches the minimum write size, the memory system transfers the write data associated with the set of write commands belonging to the first group from a write buffer in a memory of the host to a first buffer in the memory system, and writes the write data transferred to the first buffer to a first write destination block corresponding to the first stream.
    Type: Application
    Filed: April 17, 2023
    Publication date: September 21, 2023
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Publication number: 20230297514
    Abstract: A memory system includes a nonvolatile memory and a controller configured to control the nonvolatile memory based on an address conversion table. The controller is configured to generate first address mapping information indicating a first logical address range and a first physical address range, and then second address mapping information indicating a second logical address range and a second physical address range, determine whether the first and second logical address ranges are continuous and the first and second physical address ranges are continuous, upon determining non-continuity of the logical or physical address ranges, update the address conversion table based on the first address mapping information, and upon determining continuity of the logical and physical address ranges, generate integrated address mapping information using the first and second address mapping information and update the address conversion table based on the integrated address mapping information.
    Type: Application
    Filed: August 29, 2022
    Publication date: September 21, 2023
    Inventors: Takahiro KURITA, Shinichi KANNO
  • Patent number: 11762598
    Abstract: According to one embodiment, a memory system manages a plurality of first weights that correspond to the plurality of queues, and a plurality of second weights that correspond to the plurality of queues. The memory system selects a queue of a largest or smallest second weight, of the plurality of queues, as a queue of a highest priority, and starts execution of a command stored in the selected queue. The memory system updates the second weight corresponding to the selected queue by subtracting the first weight corresponding to the selected queue from the second weight corresponding to the selected queue or by adding the first weight corresponding to the selected queue to the second weight corresponding to the selected queue.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: September 19, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11762591
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks and a controller configured to write data to a plurality of write destination blocks allocated from the plurality of blocks. The controller is configured to in response to receiving a read command from a host, increment a first counter value corresponding to a first block having a block address allocated to a logical address of read target data specified by the received read command. The controller is configured to read the read target data from the first block or a buffer depending on whether the read target data is readable from the first block, and decrement the first counter value corresponding to the first block. The controller is configured to prohibit processing for transitioning a state of a block associated with an uncompleted read command to a state reusable as a new write destination block.
    Type: Grant
    Filed: August 11, 2021
    Date of Patent: September 19, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Patent number: 11762580
    Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.
    Type: Grant
    Filed: March 2, 2022
    Date of Patent: September 19, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Hideki Yoshida, Shinichi Kanno, Naoki Esaka
  • Patent number: 11755217
    Abstract: According to one embodiment, a controller manages a first set of blocks and a second set of blocks. The controller allocates a second block included in the second set of blocks to a first block included in the first set of blocks. In response to receiving one or more write command specifying the first block, the controller writes data associated with the one or more received write commands to the second block in units of a second minimum write size. When the first block is filled with data that has been written to the first block and unwritten region remains in the second block, the controller deallocates the second block from the first block, and allocates the deallocated second block to a write destination block other than the first block.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: September 12, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Publication number: 20230281118
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory, configuration unit, address translation unit, write unit and control unit. The configuration unit assigns write management areas included in a nonvolatile memory to spaces and an input space. The write management area is a unit of an area which manages the number of write. The address translation unit associates a logical address of write data with a physical address which indicates a position of the write data in the nonvolatile memory. The write unit writes the write data to the input space and then writes the write data in the input space to a space corresponding to the write data amongst the spaces. The control unit controls the spaces individually with respect to the nonvolatile memory.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 7, 2023
    Inventor: Shinichi Kanno
  • Publication number: 20230281078
    Abstract: According to one embodiment, a nonvolatile semiconductor memory device is connectable to a controller. The nonvolatile semiconductor memory device includes a cell array and a control circuit. The cell array includes a plurality of blocks. The control circuit executes program operations for a plurality of pages included in a write destination block of the blocks, in a certain program order. The write destination block is selected by the controller from the blocks. The control circuit is configured to notify a page address corresponding to a next program operation with respect to the write destination block to the controller.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Kenichiro YOSHII, Shinichi KANNO
  • Patent number: 11747989
    Abstract: According to one embodiment, a memory system manages wear of each of a plurality of blocks in a nonvolatile memory. The memory system receives, from a host, a write request including a parameter specifying a data retention term required for first data to be written. The memory system selects, from the blocks, a first block in which a data retention term estimated from the wear of the first block is longer than or equal to the specified data retention term. The memory system writes the first data to the first block.
    Type: Grant
    Filed: May 26, 2021
    Date of Patent: September 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Shinichi Kanno, Hideki Yoshida
  • Patent number: 11748256
    Abstract: According to one embodiment, a memory system includes a nonvolatile memory including plural blocks each including plural pages, and a controller. When receiving a write request designating a first logical address and a first block number from the host, the controller determines a first location in a first block having the first block number to which data from the host should be written, and writes the data from the host to the first location in the first block. The controller notifies the host of either an in-block physical address indicative of the first location, or a group of the first logical address, the first block number and the first in-block physical address.
    Type: Grant
    Filed: July 7, 2022
    Date of Patent: September 5, 2023
    Assignee: Kioxia Corporation
    Inventors: Hideki Yoshida, Shinichi Kanno
  • Patent number: 11748012
    Abstract: According to one embodiment, when receiving a write command including a first identifier of identifiers for accessing regions from a host, a memory system allocates one block of a common free block group shared by the regions as a write destination block for the region corresponding to the first identifier. When receiving a copy command including a block address of a copy source block of blocks belonging to the region corresponding to the first identifier, and an identifier of a copy destination target region indicative of the first identifier from the host, the memory system allocates one block as a copy destination block for the region corresponding to the first identifier, and copies data from the copy source block to the copy destination block.
    Type: Grant
    Filed: April 14, 2022
    Date of Patent: September 5, 2023
    Assignee: KIOXIA CORPORATION
    Inventor: Shinichi Kanno
  • Patent number: 11747984
    Abstract: A memory system connectable to a host includes a nonvolatile memory and a controller. The controller is configured to generate one or more virtual storage regions each of which is associated with a virtual machine running in the host, using physical memory regions of the nonvolatile memory, maintain a threshold value for each of said one or more virtual storage regions, determine a cumulative amount of data that have been written in each of said one or more virtual storage regions, and restrict writing of data with respect to a virtual storage region for which the cumulative amount exceeds the threshold value.
    Type: Grant
    Filed: March 16, 2021
    Date of Patent: September 5, 2023
    Assignee: Kioxia Corporation
    Inventor: Shinichi Kanno
  • Publication number: 20230273750
    Abstract: According to one embodiment, a memory system checks a first total size indicative of a sum of data lengths specified by first write commands stored in a first submission queue of a host corresponding to a first stream. When the first total size is greater than or equal to a minimum write size, the memory system fetches a set of first write commands stored in the first submission queue, transfers first write data associated with the set of first write commands from a memory of the host to the memory system, and writes the first write data into a first write destination block allocated for the first stream.
    Type: Application
    Filed: April 10, 2023
    Publication date: August 31, 2023
    Applicant: KIOXIA CORPORATION
    Inventor: Shinichi KANNO
  • Publication number: 20230267075
    Abstract: According to one embodiment, a write instructing unit instructs a data access unit to write, in a storage area of a data storage unit indicated by a first physical address, write object data, instructs a management information access unit to update address conversion information, and instructs a first access unit to update the first physical address. A compaction unit extracts a physical address of compaction object data, instructs the data access unit to read the compaction object data stored in a storage area of the data storage unit indicated by the physical address, instructs the data access unit to write the compaction object data in a storage area of the data storage unit indicated by a second physical address, instructs the management information access unit to update the address conversion information, and instructs a second access unit to update the second physical address.
    Type: Application
    Filed: May 2, 2023
    Publication date: August 24, 2023
    Applicant: KIOXIA CORPORATION
    Inventors: Kazuhiro FUKUTOMI, Kenichiro YOSHII, Shinichi KANNO, Shigehiro ASANO