Abstract: A solid-state imaging device is provided that enables miniaturization of a pixel and improvement in electrical properties of a transistor of a pixel circuit. The solid-state imaging device includes a first semiconductor layer and a second semiconductor layer. In the first semiconductor layer, a pixel including a photoelectric converter is arranged in a matrix along a plane direction. The number of the pixel is two or more. The second semiconductor layer is stacked on the first semiconductor layer on an opposite side to a light-incoming side of the pixel. In the second semiconductor layer, a first transistor electrically coupled to the pixel is provided. A gate lengthwise direction of the first transistor is inclined with respect to an arrangement direction of the pixel.

Abstract: A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.

Abstract: A solid-state imaging device (200) includes a photoelectric conversion device (211), a current-voltage conversion circuit (310), and an output circuit. The photoelectric conversion device (211) performs photoelectric conversion of incident light. The current-voltage conversion circuit (310) includes a first transistor (311) that converts an amount of electric charge generated by photoelectric conversion into a voltage signal. The output circuit includes a second transistor having an S value smaller than an S value of the first transistor (311) and generates an output signal based on the voltage signal.

Abstract: Provided is a display device with extremely high resolution, a display device with higher display quality, a display device with improved viewing angle characteristics, or a flexible display device. Same-color subpixels are arranged in a zigzag pattern in a predetermined direction. In other words, when attention is paid to a subpixel, another two subpixels exhibiting the same color as the subpixel are preferably located upper right and lower right or upper left and lower left. Each pixel includes three subpixels arranged in an L shape. In addition, two pixels are combined so that pixel units including subpixel are arranged in matrix of 3×2.

Abstract: A solid-state imaging element (200) according to the present disclosure includes a light receiving substrate (201) and a circuit board (202). The light receiving substrate (201) includes a plurality of light receiving circuits (211) in which photoelectric conversion elements are provided. The circuit board (202) is bonded to the light receiving substrate (201) and includes a plurality of address event detection circuits (231) that respectively detects voltage changes output from the photoelectric conversion elements of the plurality of light receiving circuits (211). The circuit board (202) includes a first element region (501) and a second element region (502). In the first element region (501), a first transistor (T1) driven by a first voltage (VDD1) is arranged. In the second element region (502), a second transistor (T2) driven by a second voltage (VDD2) lower than the first voltage (VDD1) is arranged.

Abstract: The present technology relates to an imaging element and an imaging device that facilitate miniaturization of pixels. The first substrate including a plurality of detection pixels that generates a voltage signal corresponding to a logarithmic value of a photocurrent, and the second substrate including a detection circuit that detects whether the change amount of the voltage signal of a detection pixel indicated by an inputted selection signal among the plurality of detection pixels exceeds a predetermined threshold or not are stacked, and an element constituting the detection circuit is disposed in each of a first region on a back surface side and a second region on a front surface side of the second substrate. The present technology can be applied to, for example, an imaging element that detects an address event for each pixel.

Abstract: To downsize an imaging element formed by stacking a plurality of semiconductor substrates. The imaging element includes a first semiconductor substrate and a second semiconductor substrate. The first semiconductor substrate includes a photoelectric conversion section that performs photoelectric conversion of incident light. The second semiconductor substrate includes a pixel circuit that generates an image signal according to a charge generated by the photoelectric conversion, an element isolating region that isolates elements of the pixel circuit, and a high impurity concentration region which is disposed below the element isolating region and having a high impurity concentration and is connected to the first semiconductor substrate in order to use a reference potential in common, with the first semiconductor substrate being stacked on a back surface side of the second semiconductor substrate.

Abstract: A semiconductor device includes a base, a first FET that includes at least two channel structure portions laminated, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.

Abstract: An apparatus and method enabling a reduction in a resistance of a conductive path electrically connecting an upper substrate and a lower substrate. The apparatus includes a first semiconductor layer with element formation regions disposed adjacent to one another via element isolation regions, each of the element formation regions having a first active element, contact regions on an element isolation region side of a front layer portion of the element formation regions, conductive pads connected to the contact regions and extending across the element isolation region, a first insulating layer, a second semiconductor layer on the first insulating layer and having a second active element, a second insulating layer covering the second semiconductor layer, and conductive plugs extending from the second insulating layer to the conductive pad, the conductive plugs including a material identical to a material of the conductive pad and formed integrally with the conductive pad.

Abstract: [Problem to be Solved] To provide a transistor and an electronic device whose characteristics are easier to control. [Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered by the gate electrode is provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.

Abstract: A semiconductor device includes a base, a first FET that includes at least two laminated channel structure portions, the channel structure portions each including a channel portion having a nanowire structure, a gate insulation film, and a gate electrode, and a second FET that includes a channel forming layer, a gate insulation layer, and a gate electrode. The first FET and the second FET are provided above the base. The channel portions of the first FET are disposed apart from each other in a laminating direction of the channel structure portions. Assuming that each of a distance between the channel portions of the first FET is a distance L1 and that a thickness of the gate insulation layer of the second FET is a thickness T2, T2?(L1/2) is satisfied.

Abstract: There is provided a solid-state imaging device including: a first semiconductor layer including a photoelectric converter and an electric charge accumulation section for each pixel, the electric charge accumulation section in which a signal electric charge generated in the photoelectric converter is accumulated; a pixel separation section that is provided in the first semiconductor layer, and partitions a plurality of the pixels from each other; a second semiconductor layer that is provided with a pixel transistor and is stacked on the first semiconductor layer, the pixel transistor that reads the signal electric charge of the electric charge accumulation section; and a first shared coupling section that is provided between the second semiconductor layer and the first semiconductor layer, and is provided to straddle the pixel separation section and is electrically coupled to a plurality of the electric charge accumulation sections.

Abstract: An imaging element according to an embodiment of the present disclosure includes a first semiconductor substrate, and a second semiconductor substrate stacked over the first semiconductor substrate with an insulating layer interposed therebetween. The first semiconductor substrate includes a photoelectric conversion section, and a charge-holding section that holds charges transferred from the photoelectric conversion section. The second semiconductor substrate includes an amplification transistor that generates a signal of a voltage corresponding to a level of charges held in the charge-holding section. The amplification transistor includes a channel region, a source region, and a drain region in a plane intersecting a front surface of the second semiconductor substrate, and includes a gate electrode being opposed to the channel region with a gate insulating film interposed therebetween and being electrically coupled to the charge-holding section.

Abstract: A semiconductor device includes a base, a first FET 10n that includes at least two channel structure portions 11n laminated, the channel structure portions 11n each including a channel portion 13n having a nanowire structure 12n, a gate insulation film, and a gate electrode 27n, and a second FET 20n that includes a channel forming layer 23n, a gate insulation layer, and a gate electrode 27n. The first FET 10n and the second FET 20n are provided above the base. The channel portions 13n of the first FET 10n are disposed apart from each other in a laminating direction of the channel structure portions 11n. Assuming that each of a distance between the channel portions 13n of the first FET 10n is a distance L1 and that a thickness of the gate insulation layer of the second FET 20n is a thickness T2, T2?(L1/2) is satisfied.

Abstract: The present technology relates to a semiconductor device and a manufacturing method that make it possible to reduce PID. The semiconductor device includes a first layer, a second layer laminated with the first layer, a conductive member that comes into contact with a lateral surface of a groove part formed in the first layer and the second layer, and first wiring that is formed in the second layer and comes into contact with a bottom surface of the groove part. The conductive member is connected to a protecting element for discharging charges accumulated inside the groove part. The present technology is applicable to, for example, the formation of a via in a silicon substrate and an interlayer film laminated with each other.

Abstract: To perform protection from damage in a semiconductor device manufacturing process while suppressing an increase in an area. A protection circuit includes at least one protection transistor. A first diffusion layer of the protection transistor is connected to a terminal of a protected circuit. A second diffusion layer of the protection transistor is connected to a ground level. A gate and a well of the protection transistor are connected to power supply lines. When receiving plasma induced damage, voltages of the second diffusion layer, the gate, and the well of the protection transistor are relatively lowered, and the protection transistor operates in a forward bias mode.

Abstract: [Problem to be Solved] To provide a transistor and an electronic device whose characteristics are easier to control. [Solution] A transistor including: a semiconductor substrate; an insulating layer provided on the semiconductor substrate; a semiconductor layer provided on the insulating layer in a protruding manner; and a gate electrode provided over a portion of the insulating layer on the semiconductor layer and the insulating layer. A middle portion of a channel region of the semiconductor layer covered by the gate electrode is provided in a shape different from a shape of at least one of ends of the channel region of the semiconductor layer.

Abstract: The present technology relates to a semiconductor device and a manufacturing method that make it possible to reduce PID. Provided is a semiconductor device including: a first layer; a second layer laminated with the first layer; a conductive member that comes into contact with a lateral surface of a groove part formed in the first layer and the second layer; and first wiring that is formed in the second layer and comes into contact with a bottom surface of the groove part, in which the conductive member is connected to a protecting element for discharging charges accumulated inside the groove part. The present technology is applicable to, for example, the formation of a via in a silicon substrate and an interlayer film laminated with each other.

Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with agate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.

Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.