Patents by Inventor Shinichi Miyake
Shinichi Miyake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10050142Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: GrantFiled: October 20, 2017Date of Patent: August 14, 2018Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi
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Publication number: 20180076312Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with agate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.Type: ApplicationFiled: November 20, 2017Publication date: March 15, 2018Inventors: Shinichi MIYAKE, Tatsuo NAKAYAMA
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Publication number: 20180061983Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: ApplicationFiled: October 20, 2017Publication date: March 1, 2018Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Yasuhiro OKAMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI
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Patent number: 9837524Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with agate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.Type: GrantFiled: November 1, 2016Date of Patent: December 5, 2017Assignee: Renesas Electronics CorporationInventors: Shinichi Miyake, Tatsuo Nakayama
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Patent number: 9831339Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: GrantFiled: June 26, 2017Date of Patent: November 28, 2017Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi
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Publication number: 20170294538Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: ApplicationFiled: June 26, 2017Publication date: October 12, 2017Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Yasuhiro OKAMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI
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Patent number: 9722062Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: GrantFiled: August 27, 2015Date of Patent: August 1, 2017Assignee: Renesas Electronics CorporationInventors: Tatsuo Nakayama, Hironobu Miyamoto, Ichiro Masumoto, Yasuhiro Okamoto, Shinichi Miyake, Hiroshi Kawaguchi
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Publication number: 20170054016Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with agate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.Type: ApplicationFiled: November 1, 2016Publication date: February 23, 2017Inventors: Shinichi MIYAKE, Tatsuo NAKAYAMA
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Publication number: 20170047437Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has an impurity-containing potential fixed layer, and a gate electrode. A drain electrode and a source electrode are formed on the opposite sides of the gate electrode. An interlayer insulation film is formed between the gate electrode and the drain electrode, and between the gate electrode and the source electrode. The concentration of the inactivating element in the portion of the potential fixed layer under the drain electrode is higher than the concentration of the inactivating element in the portion of the potential fixed layer under the source electrode. The film thickness of the portion of the interlayer insulation film between the gate electrode and the drain electrode is different from the film thickness of the portion of the interlayer insulation film between the gate electrode and the source electrode.Type: ApplicationFiled: July 22, 2016Publication date: February 16, 2017Applicant: Renesas Electronics CorporationInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI
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Patent number: 9508842Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with a gate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.Type: GrantFiled: December 6, 2015Date of Patent: November 29, 2016Assignee: Renesas Electronics CorporationInventors: Shinichi Miyake, Tatsuo Nakayama
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Publication number: 20160172474Abstract: A semiconductor device includes a buffer layer, a channel layer, a barrier layer, and agate electrode over a substrate, the gate electrode being disposed in a first opening with a gate insulating film in between, the first opening running up to the middle of the channel layer through the barrier layer. The concentration of two-dimensional electron gas in a first region on either side of a second opening that will have a channel is controlled to be lower than the concentration of two-dimensional electron gas in a second region between an end of the first region and a source or drain electrode. The concentration of the two-dimensional electron gas in the first region is thus decreased, thereby the conduction band-raising effect of polarization charge is prevented from being reduced. This prevents a decrease in threshold potential, and thus improves normally-off operability.Type: ApplicationFiled: December 6, 2015Publication date: June 16, 2016Inventors: Shinichi MIYAKE, Tatsuo NAKAYAMA
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Publication number: 20160064538Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.Type: ApplicationFiled: August 27, 2015Publication date: March 3, 2016Applicant: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Yasuhiro OKAMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI
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Patent number: 8882878Abstract: A method of producing ultra-fine metal particles of the present invention includes: blowing metal powders of raw materials into reducing flame formed by a burner 3 in a furnace 5, wherein the metal powders are melted in the flame and allowed to be in an evaporated state, to thereby obtain the spherical ultra-fine metal particles. In the present invention, the atmosphere in the furnace 5 is preferably prepared such that the CO/CO2 ratio is within a range from 0.15 to 1.2. Also, a spiral flow-forming gas is preferably blown into the furnace 5, and the oxygen ratio of the burner 3 is preferably within a range from 0.4 to 0.8. As raw materials, a metal oxide and/or a metal hydroxide which contain the same metal as the metal powders may be used together with the metal powders.Type: GrantFiled: July 8, 2008Date of Patent: November 11, 2014Assignee: Taiyo Nippon Sanso CorporationInventors: Hiroshi Igarashi, Takayuki Matsumura, Shinichi Miyake
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Patent number: 8513033Abstract: A design method of a semiconductor device includes setting an inspection region of layout data generated based on circuit data, calculating an area ratio of a first area to a second area, the first area indicating an area of the inspection region, the second area indicating a sum of a surface area of a plane that a first member contacts with a second member, the second member contacting with the first member constituting a circuit element included in the inspection region, the second member further having different heat reflective properties from the first member, and arranging a dummy element in the layout data so that the area ratio is within a predetermined range in each inspection region of the layout data.Type: GrantFiled: October 25, 2010Date of Patent: August 20, 2013Assignee: Renesas Electronics CorporationInventors: Naoyoshi Kawahara, Shinya Maruyama, Shinichi Miyake
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Patent number: 8507339Abstract: In a BiCMOS device, a device isolation film separating the bipolar transistor region from the MOS region is taller than the substrate at least where it contacts the bipolar transistor region, and is preferably taller than the same layer where it contacts the MOS transistor region. This makes it possible to maintain the processing accuracy of a MOS transistor while stabilizing the diode current characteristics of the bipolar transistor.Type: GrantFiled: November 19, 2010Date of Patent: August 13, 2013Assignee: Renesas Electronics CorporationInventors: Shinichi Miyake, Kazuaki Tsunoda
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Patent number: 8492532Abstract: A nucleic acid molecule containing nucleotide sequences that encode the capsid protein, pre-membrane protein and non-structural protein of Japanese encephalitis virus, and a nucleotide sequence that encodes the envelop protein of a second flavivirus, wherein the nucleotide sequence(s) that encode(s) the pre-membrane protein and/or non-structural protein of Japanese encephalitis virus contain(s) nucleotide mutations that produce one or more amino acid mutations that attenuate the virus.Type: GrantFiled: November 20, 2008Date of Patent: July 23, 2013Assignee: The Research Foundation for Microbial Diseases of Osaka UniversityInventors: Kouichi Morita, Takeshi Nabeshima, Shinichi Miyake, Toshiyuki Onishi, Isao Fuke, Toyokazu Ishikawa, Hideo Goda, Masahide Ishibashi, Michiaki Takahashi
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Patent number: 8393892Abstract: A burner for production of inorganic spheroidized particles according to the present invention includes a raw material powder supply path that supplies raw material powder by using oxygen or an oxygen-enriched air as a carrier gas; a powder diffusion plate having a plurality of fine holes, which is provided at a downstream end of the raw material powder supply path; a raw material diffusion chamber that is formed in a diffusion pipe provided at a downstream end of the powder diffusion plate; a fuel supply path disposed around the outer circumference of the raw material powder supply path; an oxygen supply path disposed around the outer circumference of the fuel supply path; and a combustion chamber disposed at a downstream side of the raw material diffusion chamber, which has an inside diameter increasing along the downstream direction and communicates with the fuel supply path and the oxygen supply path.Type: GrantFiled: May 30, 2007Date of Patent: March 12, 2013Assignee: Taiyo Nippon Sanso CorporationInventors: Yoshiyuki Hagihara, Kazuro Suzuki, Shinichi Miyake, Yasuyuki Yamamoto
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Publication number: 20130023618Abstract: The present invention provides a profile extrusion molding resin composition capable of forming a profile extrusion resin molded product which is excellent in strength, impact resistance, heat resistance, scratch resistance, surface appearance and shaping property.Type: ApplicationFiled: January 24, 2011Publication date: January 24, 2013Inventors: Shinichi Miyake, Tadashi Nagahara
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Patent number: 8062406Abstract: A process for producing metallic ultra-fine powder, which can use a raw material which is spread over a wide range, and control freely the grain size of the metallic powder to be produced, at low cost and high safety. The process for producing the metallic ultra fine powder consists of using a burner and a furnace which can generate a high temperature reductive atmosphere, and an apparatus for separating gas which is generated in the furnace from powder to recover the powder. The burner has a function of blowing a powdery metallic compound as a raw material into a high temperature reductive flame. The raw material powder is efficiently heated in airflow of a high temperature reductive flame, thereby being reduced rapidly into metallic ultra-fine powder. At this time, the grain size of the metallic ultra-fine powder is controlled by adjusting the oxygen ratio (i.e.Type: GrantFiled: December 22, 2005Date of Patent: November 22, 2011Assignee: Taiyo Nippon Sanso CorporationInventors: Hiroshi Igarashi, Takayuki Matsumura, Shinichi Miyake
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Publication number: 20110256250Abstract: A process for producing metallic ultra-fine powder, which can use a raw material which is spread over a wide range, and control freely the grain size of the metallic powder to be produced, at low cost and high safety. The process for producing the metallic ultra fine powder consists of using a burner and a furnace which can generate a high temperature reductive atmosphere, and an apparatus for separating gas which is generated in the furnace from powder to recover the powder. The burner has a function of blowing a powdery metallic compound as a raw material into a high temperature reductive flame. The raw material powder is efficiently heated in airflow of a high temperature reductive flame, thereby being reduced rapidly into metallic ultra-fine powder. At this time, the grain size of the metallic ultra-fine powder is controlled by adjusting the oxygen ratio (i.e.Type: ApplicationFiled: June 27, 2011Publication date: October 20, 2011Applicant: TAIYO NIPPON SANSO CORPORATIONInventors: Hiroshi Igarashi, Takayuki Matsumura, Shinichi Miyake