Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

Abstract: Nanosheets 21 to 24 are formed in line in this order in the X direction, and nanosheets 25 to 28 are formed in line in this order in the X direction. Faces of the nanosheets 21, 23, 25, and 27 on the first side in the X direction are exposed from gate interconnects 30, 33, 35, and 36, respectively. Faces of the nanosheets 22, 24, 26, and 28 on the second side in the X direction are exposed from gate interconnects 33, 34, 36, and 39, respectively.

Abstract: In a ROM cell using a vertical nanowire (VNW) FET, the gate of the VNW FET is connected with a word line (WL), the bottom thereof is connected with a bit line (BL), and the top thereof is selectively connected with a ground potential line. The bottom of the VNW FET of the ROM cell is connected to the bit line (BL) irrespective of the data stored in the ROM cell.

Abstract: A layout structure of a ROM cell using a complementary FET (CFET) is provided. The ROM cell includes first and second three-dimensional transistors. The second transistor is formed above the first transistor, and the channel portions of the first and second transistors overlap each other. First data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the first transistor and a ground power supply line, and second data is stored in the ROM cell depending on the presence or absence of connection between a local interconnect connected to the source of the second transistor and a ground power supply line.

Abstract: Transistors N1, N5 corresponding to a drive transistor PD1 are formed in a cell lower part and a cell upper part, respectively, and transistors N2, N6 corresponding to a drive transistor PD2 are formed in the cell lower part and the cell upper part, respectively. A transistor P1 corresponding to a load transistor PU2 is formed in the cell lower part, and a transistor P2 corresponding to a load transistor PU1 is formed in the cell upper part.

Abstract: A static random access memory (SRAM) cell has first to sixth transistors that are vertical nanowire (VNW) FETs. The second and fifth transistors are placed side by side sequentially on one side in the X direction of the first transistor. The fourth and sixth transistors are placed side by side sequentially on the other side in the X direction of the third transistor. The first and third transistors are placed side by side in the Y direction.

Abstract: In an SRAM cell using vertical nanowire (VNW) FETs, transistors (PD1, PD2) constituting a drive transistor are placed on both sides of a transistor (PU1) in an X direction, and transistors (PD3, PD4) constituting a drive transistor are placed on both sides of a transistor (PU2) in the X direction. An access transistor (PG1) is placed on one-hand side in the X direction of the transistor (PU1), and an access transistor (PG2) is placed on the other-hand side in the X direction of the transistor (PU1).

Abstract: In a ROM cell using a vertical nanowire (VNW) FET, the gate of the VNW FET is connected with a word line (WL), the bottom thereof is connected with a bit line (BL), and the top thereof is selectively connected with a ground potential line. The bottom of the VNW FET of the ROM cell is connected to the bit line (BL) irrespective of the data stored in the ROM cell.

Abstract: A semiconductor memory device includes a memory cell including a first memory unit and a second memory unit which are coupled to a complementary bit line pair, an operation controller configured to successively select the first memory unit and the second memory unit, during a read operation which reads data from the memory cell, a first readout unit coupled to one of the bit line pair, and configured to judge a logical value of the data read from the selected first memory unit onto the one of the bit line pair, and a second readout unit coupled to the other of the bit line pair, and configured to judge a logical value of the data read from the selected second memory unit onto the other of the bit line pair.

Abstract: In an SRAM cell using vertical nanowire (VNW) FETs, transistors (PD1, PD2) constituting a drive transistor are placed on both sides of a transistor (PU1) in an X direction, and transistors (PD3, PD4) constituting a drive transistor are placed on both sides of a transistor (PU2) in the X direction. An access transistor (PG1) is placed on one-hand side in the X direction of the transistor (PU1), and an access transistor (PG2) is placed on the other-hand side in the X direction of the transistor (PU1).

Abstract: A static random access memory (SRAM) cell has first to sixth transistors that are vertical nanowire (VNW) FETs. The second and fifth transistors are placed side by side sequentially on one side in the X direction of the first transistor. The fourth and sixth transistors are placed side by side sequentially on the other side in the X direction of the third transistor. The first and third transistors are placed side by side in the Y direction.

Abstract: Disclosed is a semiconductor storage device having a dual-port SRAM cell with a smaller area and low-current consumption and securing a good static noise margin. The semiconductor storage device includes a memory cell circuit constituting the dual port SRAM cell comprised of six transistors. When driving the first or second word line, a word line driver circuit lowers a high-level voltage which is to be output to the driven word line such that the high-level voltage is lower than a high-level voltage which is to be output to both of the first and second word lines when driving both the first and second word lines.

Abstract: A semiconductor memory device includes a memory cell including a first memory unit and a second memory unit which are coupled to a complementary bit line pair, an operation controller configured to successively select the first memory unit and the second memory unit, during a read operation which reads data from the memory cell, a first readout unit coupled to one of the bit line pair, and configured to judge a logical value of the data read from the selected first memory unit onto the one of the bit line pair, and a second readout unit coupled to the other of the bit line pair, and configured to judge a logical value of the data read from the selected second memory unit onto the other of the bit line pair.

Abstract: Disclosed is a semiconductor storage device having a dual-port SRAM cell with a smaller area and low-current consumption and securing a good static noise margin. The semiconductor storage device includes a memory cell circuit constituting the dual port SRAM cell comprised of six transistors. When driving the first or second word line, a word line driver circuit lowers a high-level voltage which is to be output to the driven word line such that the high-level voltage is lower than a high-level voltage which is to be output to both of the first and second word lines when driving both the first and second word lines.

Abstract: A semiconductor device includes a circuit block that is switchable between selection and non-selection, and a leakage current control circuit disposed between the circuit block and a first power supply line. The leakage current control circuit includes a first transistor disposed between the circuit block and the first power supply line, and a resistor device disposed between the circuit block and the first power supply line.

Abstract: There are provided a ring oscillator having a plurality of delay circuits to be ring-connected. At least one of the plurality of delay circuits has a delay element formed in a layout region including the same layout shape as the layout shape of an SRAM cell, and a path circuit connected in parallel to the delay element. The delay element outputs an output signal to a delay circuit in the next stage within the plurality of delay circuits in response to one of rise transition and fall transition of a signal input to the input terminal of the delay element from a delay circuit in the previous stage within the plurality of delay circuits. The path circuit outputs an output signal to the delay circuit in the next stage in response to the transition other than the one transition.

Abstract: A semiconductor device includes a circuit block that is switchable between selection and non-selection, and a leakage current control circuit disposed between the circuit block and a first power supply line. The leakage current control circuit includes a first transistor disposed between the circuit block and the first power supply line, and a resistor device disposed between the circuit block and the first power supply line.

Abstract: A static RAM includes: a plurality of word lines; a plurality of pairs of local bit lines; a plurality of memory cells arranged in correspondence with intersections of the plurality of pairs of local bit lines and the plurality of word lines; a capacitance shared circuit arranged for each of the plurality of pairs of local bit lines; a common connection line connecting the plurality of capacitance shared circuits; and a pair of global bit lines connected to the plurality of pairs of local bit lines, wherein the capacitance shared circuit includes two N-channel transistors connected between the pair of local bit lines and the common connection line corresponding to each other.

Abstract: A semiconductor memory includes a real memory cell; a sense amplifier configured to amplify data read from the real memory cell in response to activation of a sense amplifier enable signal; a replica circuit including a plurality of replica units connected in series, each of replica units including a plurality of dummy memory cells connected in parallel, wherein one of dummy memory cells of one of replica units is accessed in response to data which is read from one of dummy memory cells of one of replica units of a prior stage; and an operation control circuit configured to activate a dummy access signal to access one of dummy memory cells of one of replica units of a first stage in response to a read command, and to activate the sense amplifier enable signal in response to data read from one of replica units of a last stage.