Patents by Inventor Shinichi Nakagawa
Shinichi Nakagawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7910431Abstract: On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural contact plugs connected respectively to a control gate of the nonvolatile memory cell, a source or a drain of the nMOS transistor, and a source or a drain of the pMOS transistor. Thereafter, there is formed a single-layer wiring connecting the control gate to the sources or drains of the nMOS transistor and the pMOS transistor via the plural contact plugs.Type: GrantFiled: April 30, 2008Date of Patent: March 22, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Koji Takahashi, Shinichi Nakagawa
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Publication number: 20110059603Abstract: Disclosed is a method of manufacturing a semiconductor device, which includes exposing a photoresist using an exposing mask provided with a light-shielding pattern having two or more narrow width portions, developing the photoresist to form a plurality of stripe-shaped resist patterns, selectively etching a first conductive film using the resist pattern as a mask, forming an intermediate insulating film on the first conductive film, forming a second conductive film on the intermediate insulating film, and forming, by patterning the first conductive film, the intermediate insulating film, and the second conductive film, a flash memory cell and a structure constructed by forming a lower conductor pattern, a segment of the intermediate insulating film, and a dummy gate electrode in this stacking order.Type: ApplicationFiled: November 16, 2010Publication date: March 10, 2011Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Shinichi Nakagawa, Itsuro Sannomiya
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Patent number: 7859045Abstract: Disclosed is a method of manufacturing a semiconductor device, which includes exposing a photoresist using an exposing mask provided with a light-shielding pattern having two or more narrow width portions, developing the photoresist to form a plurality of stripe-shaped resist patterns, selectively etching a first conductive film using the resist pattern as a mask, forming an intermediate insulating film on the first conductive film, forming a second conductive film on the intermediate insulating film, and forming, by patterning the first conductive film, the intermediate insulating film, and the second conductive film, a flash memory cell and a structure constructed by forming a lower conductor pattern, a segment of the intermediate insulating film, and a dummy gate electrode in this stacking order.Type: GrantFiled: June 16, 2008Date of Patent: December 28, 2010Assignee: Fujitsu Semiconductor LimitedInventors: Shinichi Nakagawa, Itsuro Sannomiya
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Patent number: 7767523Abstract: A non-volatile semiconductor memory device includes: a nonvolatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of the gate electrode; a peripheral circuit area including single-layer gate electrodes made of the same layer as the control gate; and a first border area including: a first isolation region formed in the semiconductor substrate for isolating the non-volatile memory area and peripheral circuit area; a first conductive pattern including a portion made of the same layer as the control gate and formed above the isolation region; and a first redundant insulating side wall made of the same layer as the first insulating side wall and formed on the side wall of the first conductive pattern on the side of the non-volatile memory area.Type: GrantFiled: February 4, 2009Date of Patent: August 3, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Shinichi Nakagawa
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Patent number: 7759725Abstract: Disclosed is a method of manufacturing a semiconductor device, including the steps of: forming on a second insulating film a first resist pattern having a first window; employing the first resist pattern as an etching mask to form first openings exposed from contact regions CR; forming, on a second conductive film, a second resist pattern having first resist portions; employing the second resist pattern as an etching mask to form first and second conductors, a floating gate and a control gate; forming a third resist pattern in regions I, II and III; and employing the third resist pattern as an etching mask to remove the portions of the second conductors under second windows.Type: GrantFiled: April 27, 2007Date of Patent: July 20, 2010Assignee: Fujitsu Semiconductor LimitedInventor: Shinichi Nakagawa
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Publication number: 20100141218Abstract: A charging circuit that prevents a system abnormality caused by removal of a battery. The charging circuit includes a constant voltage charge controller which detects charge voltage and performs a constant voltage charging operation. A constant current charge controller detects charge current and performs a constant current charging operation. A controller controls the constant voltage charge controller to perform the constant voltage charging operation during a period from when the charge voltage reaches a fully charged voltage to when the charge current decreases to a charge completion current. The controller suspends charging the battery when the constant voltage charging operation is being performed and detects whether or not the battery is coupled to the charging circuit based on the charge voltage during the charging suspension.Type: ApplicationFiled: February 18, 2010Publication date: June 10, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Shinichi NAKAGAWA
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Publication number: 20100090673Abstract: A power supply apparatus is provided which includes: a first switch provided between an inductor and a terminal to which a reference voltage is applied; a second switch provided between the inductor and an output terminal; a first comparator circuit that compares an input voltage with a first comparison voltage; a signal generating circuit that outputs a frequency signal according to an output from the first comparator circuit; and a first control circuit that controls the first and second switches based on an output from the signal generating circuit to control an electrical current flowing into the inductor.Type: ApplicationFiled: December 13, 2009Publication date: April 15, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Shinichi NAKAGAWA, Masahiro Natsume, Katsuyuki Yasukouchi
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Publication number: 20090191700Abstract: A non-volatile semiconductor memory device includes: a nonvolatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of the gate electrode; a peripheral circuit area including single-layer gate electrodes made of the same layer as the control gate; and a first border area including: a first isolation region formed in the semiconductor substrate for isolating the non-volatile memory area and peripheral circuit area; a first conductive pattern including a portion made of the same layer as the control gate and formed above the isolation region; and a first redundant insulating side wall made of the same layer as the first insulating side wall and formed on the side wall of the first conductive pattern on the side of the non-volatile memory area.Type: ApplicationFiled: February 4, 2009Publication date: July 30, 2009Applicant: FUJITSU MICROELECTRONICS LIMITEDInventor: Shinichi Nakagawa
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Patent number: 7560329Abstract: The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the side wall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate electrode 112 with the sidewall spacer 116 formed on, and an oxide film 115 formed between the sidewall spacer 116 and the sidewall spacer 144, and the semiconductor substrate 10. The film thickness of the oxide film 115 between the sidewall spacer 144 and the semiconductor substrate 10 is thinner than the film thickness of the oxide film 115 between the sidewall spacer 116 and the semiconductor substrate 10.Type: GrantFiled: July 13, 2007Date of Patent: July 14, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Shinichi Nakagawa
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Patent number: 7541236Abstract: On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural contact plugs connected respectively to a control gate of the nonvolatile memory cell, a source or a drain of the nMOS transistor, and a source or a drain of the PMOS transistor. Thereafter, there is formed a single-layer wiring connecting the control gate to the sources or drains of the nMOS transistor and the pMOS transistor via the plural contact plugs.Type: GrantFiled: December 23, 2004Date of Patent: June 2, 2009Assignee: Fujitsu LimitedInventors: Koji Takahashi, Shinichi Nakagawa
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Patent number: 7539963Abstract: The semiconductor group comprises a first semiconductor device including a first design macro and a nonvolatile memory, and a second semiconductor device including a second design macro having identity with the first design macro and including no nonvolatile memory. The first design macro includes a first active region and a first device isolation region formed on a first semiconductor substrate. The second design macro includes a second active region and a second device isolation region formed on a second semiconductor substrate. A curvature radius of an upper end of the first active region in a cross section is larger than a curvature radius of an upper end of the second active region in a cross section. A difference in height between a surface of the first active region and a surface of the first device isolation region is larger than a difference in height between a surface of the second active region and a surface of the device isolation region.Type: GrantFiled: October 21, 2004Date of Patent: May 26, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Taiji Ema, Hideyuki Kojima, Toru Anezaki, Shinichi Nakagawa
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Patent number: 7504688Abstract: A non-volatile semiconductor memory device includes: a non-volatile memory area including gate electrodes, each including stack of a floating gate, an inter-electrode insulating film and a control gate, and having first insulating side walls formed on side walls of the gate electrode; a peripheral circuit area including single-layer gate electrodes made of the same layer as the control gate; and a first border area including: a first isolation region formed in the semiconductor substrate for isolating the non-volatile memory area and peripheral circuit area; a first conductive pattern including a portion made of the same layer as the control gate and formed above the isolation region; and a first redundant insulating side wall made of the same layer as the first insulating side wall and formed on the side wall of the first conductive pattern on the side of the non-volatile memory area.Type: GrantFiled: August 11, 2005Date of Patent: March 17, 2009Assignee: Fujitsu Microelectronics LimitedInventor: Shinichi Nakagawa
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Publication number: 20080283900Abstract: Disclosed is a method of manufacturing a semiconductor device, which includes exposing a photoresist using an exposing mask provided with a light-shielding pattern having two or more narrow width portions, developing the photoresist to form a plurality of stripe-shaped resist patterns, selectively etching a first conductive film using the resist pattern as a mask, forming an intermediate insulating film on the first conductive film, forming a second conductive film on the intermediate insulating film, and forming, by patterning the first conductive film, the intermediate insulating film, and the second conductive film, a flash memory cell and a structure constructed by forming a lower conductor pattern, a segment of the intermediate insulating film, and a dummy gate electrode in this stacking order.Type: ApplicationFiled: June 16, 2008Publication date: November 20, 2008Applicant: FUJITSU LIMITEDInventors: Shinichi NAKAGAWA, Itsuro SANNOMIYA
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Publication number: 20080257732Abstract: There is provided a gas sensor, including a gas sensing film formed of an oxide semiconductor material and a gas-permeable protection layer formed of oxide particles and arranged on the gas sensing film. The oxide particles of the protection layer have an average particle size of 500 nm or smaller.Type: ApplicationFiled: January 16, 2008Publication date: October 23, 2008Applicant: NGK SPARK PLUG CO., LTD.Inventors: Yoshihiro NAKANO, Shinichi Nakagawa, Yuichi Koyama, Takio Kojima
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Publication number: 20080220573Abstract: On a surface of a Si substrate, a nonvolatile memory cell, an nMOS transistor, and a pMOS transistor are formed, and thereafter an interlayer insulation film covering the nonvolatile memory cell, the nMOS transistor, and the pMOS transistor is formed. Next, in the interlayer insulation film, there are formed plural contact plugs connected respectively to a control gate of the nonvolatile memory cell, a source or a drain of the nMOS transistor, and a source or a drain of the pMOS transistor. Thereafter, there is formed a single-layer wiring connecting the control gate to the sources or drains of the nMOS transistor and the pMOS transistor via the plural contact plugs.Type: ApplicationFiled: April 30, 2008Publication date: September 11, 2008Applicant: FUJITSU LIMITEDInventors: Koji Takahashi, Shinichi Nakagawa
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Patent number: 7412871Abstract: There is provided an oxidizing gas sensor that includes an insulating substrate, a gas sensing layer laminated on the insulating substrate and substantially made of tin oxide so as to make resistance changes in response to concentration variations in oxidizing gas and a plurality of catalyst grains applied to a surface of the gas sensing layer and substantially made of gold, wherein 20% or more of the catalyst grains have an aspect ratio of 2.0 or greater when viewed at from the surface of the gas sensing layer.Type: GrantFiled: February 23, 2006Date of Patent: August 19, 2008Assignee: NGK Spark Plug Co., Ltd.Inventors: Yoshihiro Nakano, Masahito Kida, Shinichi Nakagawa, Takio Kojima
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Patent number: 7332261Abstract: A phthalocyanine compound represented by the following general formula (I) and the mixture thereof, and an optical recording medium containing the compound/mixture in its recording layer. wherein in formula (I), M is two hydrogen atoms, a divalent metal atom, a mono-substituted trivalent metal atom, a di-substituted tetravalent metal atom, or an oxymetal, and L1, L2, L3 and L4 are each independently formula (a), formula (b), or formula (c): wherein X, Y, Z and R are defined.Type: GrantFiled: February 14, 2003Date of Patent: February 19, 2008Assignee: Ciba Specialty Chemicals CorporationInventors: Kazuhiro Seino, Shinichi Nakagawa, Tsutami Misawa, Satoshi Kinoshita, Akihiro Kosaka, Hiroshi Terao, Yojiro Kumagae
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Patent number: 7307332Abstract: The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the sidewall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate electrode 112 with the sidewall spacer 116 formed on, and an oxide film 115 formed between the sidewall spacer 116 and the sidewall spacer 144, and the semiconductor substrate 10. The film thickness of the oxide film 115 between the sidewall spacer 144 and the semiconductor substrate 10 is thinner than the film thickness of the oxide film 115 between the sidewall spacer 116 and the semiconductor substrate 10.Type: GrantFiled: June 22, 2004Date of Patent: December 11, 2007Assignee: Fujitsu LimitedInventor: Shinichi Nakagawa
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Publication number: 20070259491Abstract: The semiconductor device comprises a gate electrode 112 formed over a semiconductor substrate 10, a sidewall spacer 116 formed on the side wall of the gate electrode 112, a sidewall spacer 144 formed on the side wall of the gate electrode 112 with the sidewall spacer 116 formed on, and an oxide film 115 formed between the sidewall spacer 116 and the sidewall spacer 144, and the semiconductor substrate 10. The film thickness of the oxide film 115 between the sidewall spacer 144 and the semiconductor substrate 10 is thinner than the film thickness of the oxide film 115 between the sidewall spacer 116 and the semiconductor substrate 10.Type: ApplicationFiled: July 13, 2007Publication date: November 8, 2007Applicant: FUJITSU LIMITEDInventor: Shinichi Nakagawa
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Patent number: D563278Type: GrantFiled: August 11, 2006Date of Patent: March 4, 2008Assignee: Nissan Motor Co., Ltd.Inventors: Shinichi Nakagawa, Shinichiro Irie