Abstract: A solid-state imaging apparatus includes a plurality of high-sensitivity pixels that are arranged in a matrix, and perform a photoelectric conversion at a predetermined sensitivity; a plurality of low-sensitivity pixels that are arranged in a matrix in gaps between the plurality of high-sensitivity pixels, and perform a photoelectric conversion at a lower sensitivity than the predetermined sensitivity; and a signal processor that generates a pixel signal by (i) detecting a difference signal between a signal from the plurality of high-sensitivity pixels and a signal from the plurality of low-sensitivity pixels, and (ii) correcting the signal from the plurality of high-sensitivity pixels using the difference signal.

Abstract: A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

Abstract: A solid-state imaging apparatus includes a plurality of high-sensitivity pixels that are arranged in a matrix, and perform a photoelectric conversion at a predetermined sensitivity; a plurality of low-sensitivity pixels that are arranged in a matrix in gaps between the plurality of high-sensitivity pixels, and perform a photoelectric conversion at a lower sensitivity than the predetermined sensitivity; and a signal processor that generates a pixel signal by (i) detecting a difference signal between a signal from the plurality of high-sensitivity pixels and a signal from the plurality of low-sensitivity pixels, and (ii) correcting the signal from the plurality of high-sensitivity pixels using the difference signal.

Abstract: A solid-state imaging apparatus includes a pixel array, a column processor, and a test signal generating circuit that generates a first digital signal for testing purposes. The test signal generating circuit generates the first digital signal within one horizontal scanning period. The column processor converts a first analog signal, that is converted from the first digital signal, to a second digital signal within the one horizontal scanning period.

Abstract: In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (7, 8) based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (9). A test can be performed by supplying a test signal in place of the input analog signal. A control portion (14a) performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal.

Abstract: Multiple stages sequentially convert respective input analog signals to partial digital data. Each stage includes: a partial A/D converter; a partial D/A converter; an adder that adds/subtracts the analog signal from the previous stage and an output from the partial D/A converter; and a gain amplifier that amplifies an output of the adder and supplies to the next stage. The pipelined A/D converter further includes: a correction value adding unit that adds a correction value to the output from the decoder unit; a correction value calculating unit that, based on the output from the correction value adding unit, calculates an error between the median of the output data and an ideal median at two points in the stage input/output characteristics, saves the calculated value as the correction value and supplies it to the correction value adding unit; and a control unit that controls the above units so as to perform the correction operation.

Abstract: Multiple stages sequentially convert respective input analog signals to partial digital data. Each stage includes: a partial A/D converter; a partial D/A converter; an adder that adds/subtracts the analog signal from the previous stage and an output from the partial D/A converter; and a gain amplifier that amplifies an output of the adder and supplies to the next stage. The pipelined A/D converter further includes: a correction value adding unit that adds a correction value to the output from the decoder unit; a correction value calculating unit that, based on the output from the correction value adding unit, calculates an error between the median of the output data and an ideal median at two points in the stage input/output characteristics, saves the calculated value as the correction value and supplies it to the correction value adding unit; and a control unit that controls the above units so as to perform the correction operation.

Abstract: In each stage, a digital signal corresponding to a portion of bits is generated from an input analog signal, an analog reference signal is generated by a DA conversion portion (7, 8) based on the digital signal, and a remainder operation on the input analog signal is performed by a remainder operation portion (9). A test can be performed by supplying a test signal in place of the input analog signal. A control portion (14a) performs control, in a test mode, to stop supply of the input analog signal to the remainder operation portion and stop the reference voltage selection of the DA conversion portion based on the digital signal, while performing reference voltage selection based on a DA conversion control signal for use in testing, thereby supplying the remainder operation portion with the test signal composed of predetermined one of the reference voltages, in place of the input analog signal, and the analog reference signal.

Abstract: In each of a plurality of stages, an input analog signal is quantized, so that a digital signal corresponding to each part of bits is generated. ADA conversion portion generates an analog reference signal based on the digital signal, and a remainder operation portion performs addition/subtraction and amplification by a predetermined factor with respect to the input analog signal. Then, the signal thus obtained is supplied to a subsequent stage. The DA conversion portion in the first stage where A/D conversion of a plurality of bits is performed includes primary voltage supply portions capable of outputting a reference voltage at one of a plurality of levels, and an auxiliary voltage supply portion capable of outputting a reference voltage at an auxiliary level different from the above-described level. The respective voltage supply portions selectively output the reference voltages based on a digital signal generated by an AD conversion portion.

Abstract: In each of a plurality of stages, an input analog signal is quantized, so that a digital signal corresponding to each part of bits is generated. A DA conversion portion generates an analog reference signal based on the digital signal, and a remainder operation portion performs addition/subtraction and amplification by a predetermined factor with respect to the input analog signal. Then, the signal thus obtained is supplied to a subsequent stage. The DA conversion portion in the first stage where A/D conversion of a plurality of bits is performed includes primary voltage supply portions capable of outputting a reference voltage at one of a plurality of levels, and an auxiliary voltage supply portion capable of outputting a reference voltage at an auxiliary level different from the above-described level. The respective voltage supply portions selectively output the reference voltages based on a digital signal generated by an AD conversion portion.

Abstract: When the operating speed of a switched capacitor circuit is accelerated, the timing of the clock signals regulating switched capacitor circuit operation can be disrupted by the effects of variation introduced by the manufacturing process as well as parasitic resistance and parasitic capacitance on signal traces. A control signal generating unit adjusts the timing of the bottom plate sampling period and non-overlapping period of the clock signals supplied to operate the switched capacitor circuit, thus avoiding disrupting the control signal timing and affording a switched capacitor circuit without increasing the area of the logic devices that set the bottom plate sampling period and non-overlapping period.

Abstract: The present invention provides a pipeline A/D converter having resolution, allowable conversion processing rate and power consumption satisfying the requests of a system incorporating the pipeline A/D converter. The pipeline A/D converter in accordance with the present invention comprises a control section for outputting a control signal according to the operation state of an apparatus incorporating the pipeline A/D converter, and a pipeline A/D conversion section, the resolution and/or allowable conversion processing rate of which are switched by switching the capacitance in a built-in operational amplifier according to the control signal.

Abstract: An analog circuit includes a pulse control circuit for outputting pulse signals for operating component circuits based on reference pulse signals for driving an image sensor, a noise reduction circuit that is operated in accordance with a pulse signal of a horizontal drive frequency output from the pulse control circuit to reduce noise present in image signals output from the image sensor, a gain variable amplifier for adjusting an amplitude of signals output by the noise reduction circuit, an AD converter for converting the output signals of the gain variable amplifier into digital signals and output these digital signals, a clamp circuit that is operated in accordance with a pulse signal at a horizontal drive frequency output from the pulse control circuit to perform feedback control of the digital signals output by the AD converter, and a frequency-dependent bias circuit that supplies a current amount corresponding to the frequency of at least one kind of pulse signal from among the reference pulse signals

Abstract: (a) The luminance levels of the optical black part pixels included in the output signal of an image sensor are detected and digitized, (b) the digitized luminance levels of the optical black part pixels are averaged, (c) the number of pixels on which averaging is performed is counted, (d) a control signal is generated when the count value of the number of pixels reaches a predetermined value, (e) the black level of the output signal of the image sensor is determined from the averaged luminance level in response to the control signal, and (f) the luminance levels of the effective part pixels included in the output signal of the image sensor whose black level is determined are detected and digitized.

Abstract: A pipeline A/D converter of the present invention includes a plurality of stages each operating for A/D conversion and a digital computing portion that outputs an A/D converted signal based on a digital signal output from each of the stages. In each of the stages, an analog signal from the preceding stage is sampled by passive elements C1 and C2 in a first period, and one of the passive elements is used as a feedback element in a second period to perform adding/subtracting with respect to the signal sampled by the other passive element. By the control from the digital computing portion, a test signal Tink is used instead of an analog output signal Vo(k?1), and a unique conversion-error value is detected and corrected based on the digital signal obtained by the operation of each of the stages. It is possible to obtain a high-resolution A/D convert that can suppress a conversion error caused by the relative error of capacitors used for analog signal processing without decreasing the speed of A/D conversion.

Abstract: The present invention provides a pipeline A/D converter having resolution, allowable conversion processing rate and power consumption satisfying the requests of a system incorporating the pipeline A/D converter. The pipeline A/D converter in accordance with the present invention comprises a control section for outputting a control signal according to the operation state of an apparatus incorporating the pipeline A/D converter, and a pipeline A/D conversion section, the resolution and/or allowable conversion processing rate of which are switched by switching the capacitance in a built-in operational amplifier according to the control signal.

Abstract: The present invention provides a pipeline A/D converter having resolution, allowable conversion processing rate and power consumption satisfying the requests of a system incorporating the pipeline A/D converter. The pipeline A/D converter in accordance with the present invention comprises a control section for outputting a control signal according to the operation state of an apparatus incorporating the pipeline A/D converter, and a pipeline A/D conversion section, the resolution and/or allowable conversion processing rate of which are switched by switching the capacitance in a built-in operational amplifier according to the control signal.

Abstract: When the operating speed of a switched capacitor circuit is accelerated, the timing of the clock signals regulating switched capacitor circuit operation can be disrupted by the effects of variation introduced by the manufacturing process as well as parasitic resistance and parasitic capacitance on signal traces. A control signal generating unit adjusts the timing of the bottom plate sampling period and non-overlapping period of the clock signals supplied to operate the switched capacitor circuit, thus avoiding disrupting the control signal timing and affording a switched capacitor circuit without increasing the area of the logic devices that set the bottom plate sampling period and non-overlapping period.

Abstract: A pipeline A/D converter of the present invention includes a plurality of stages each operating for A/D conversion and a digital computing portion that outputs an A/D converted signal based on a digital signal output from each of the stages. In each of the stages, an analog signal from the preceding stage is sampled by passive elements C1 and C2 in a first period, and one of the passive elements is used as a feedback element in a second period to perform adding/subtracting with respect to the signal sampled by the other passive element. By the control from the digital computing portion, a test signal Tink is used instead of an analog output signal Vo(k?1), and a unique conversion-error value is detected and corrected based on the digital signal obtained by the operation of each of the stages. It is possible to obtain a high-resolution A/D convert that can suppress a conversion error caused by the relative error of capacitors used for analog signal processing without decreasing the speed of A/D conversion.

Abstract: A phase adjustment device which adjusts a phase difference between a first output pulse signal and a second output pulse signal according to a phase difference between a first input pulse signal and a second input pulse signal, the phase adjustment device including: a first selection unit which selects one of the first input pulse signal and an adjustment pulse signal that is used for adjustment; a second selection unit which selects one of the second input pulse signal and the adjustment pulse signal; a first delay unit which delays the signal selected by the second selection unit, and a delay amount of the first delay unit is adjustable; a first output unit which outputs, as the first output pulse signal, the signal selected by the first selection unit; a second output unit which outputs, as the second output pulse signal, the signal delayed by the first delay unit; and a phase adjustment unit which adjusts the delay amount so as to equalize phases of the first output pulse signal and the second output puls