Abstract: In a CCD solid-state image pick-up device according to the present invention, a solid-state image pick-up circuit formed by a sensor part, a horizontal transfer register part and a floating diffusion amplifier converts a photo signal into a voltage signal and outputs the voltage signal, and a voltage-current conversion circuit converts the voltage signal output from the solid-state image pick-up circuit into a current signal. A current-driven black signal component detect/remove circuit then removes a black signal component from the current signal output from the CCD solid-state image pick-up device, and an image signal component alone is output as a current image signal. A current-voltage conversion circuit converts the current image signal into a voltage image signal.

Abstract: An analog circuit includes a pulse control circuit for outputting pulse signals for operating component circuits based on reference pulse signals for driving an image sensor, a noise reduction circuit that is operated in accordance with a pulse signal of a horizontal drive frequency output from the pulse control circuit to reduce noise present in image signals output from the image sensor, a gain variable amplifier for adjusting an amplitude of signals output by the noise reduction circuit, an AD converter for converting the output signals of the gain variable amplifier into digital signals and output these digital signals, a clamp circuit that is operated in accordance with a pulse signal at a horizontal drive frequency output from the pulse control circuit to perform feedback control of the digital signals output by the AD converter, and a frequency-dependent bias circuit that supplies a current amount corresponding to the frequency of at least one kind of pulse signal from among the reference pulse signals

Abstract: Two capacitors in a variable stage are controlled from outside to function as a feedback capacitor and a sampling capacitor, respectively. With a test signal being supplied to the variable stage from an input selecting section, a stage evaluation section estimates an error in the output of the variable stage based on a difference between the digital outputs of an output correction section produced in two situations in which the functions of the two capacitors in the variable stage are switched. A correction value calculation section calculates a digital correction value for each variable stage based on the estimated error and an intermediate output of a digital calculation section. The output correction section corrects the digital output of the digital calculation section based on these digital correction values.

Abstract: The present invention provides a pipeline A/D converter having resolution, allowable conversion processing rate and power consumption satisfying the requests of a system incorporating the pipeline A/D converter. The pipeline A/D converter in accordance with the present invention comprises a control section for outputting a control signal according to the operation state of an apparatus incorporating the pipeline A/D converter, and a pipeline A/D conversion section, the resolution and/or allowable conversion processing rate of which are switched by switching the capacitance in a built-in operational amplifier according to the control signal.

Abstract: A linear-in-dB variable gain amplifier is provided, which approximates gain control characteristics to approximate Linear-in-dB characteristics. A gain G is determined so as to have approximate Linear-in-dB characteristics passing through the maximum value, minimum value, and intermediate value of the gain by a capacitance ratio between capacitance of a higher order capacitor string composed of n capacitors or a lower order capacitor string composed of m capacitors selectively connected in parallel to an input fixed capacitor, and capacitance of a lower order capacitor string, a first correction capacitor string composed of n capacitors, or a second correction capacitor string composed of m capacitors selectively connected in parallel to a feedback loop fixed capacitor, in accordance with a gain control signal (Code) of lower order m bits and higher order n bits.

Abstract: A linear-in-db variable gain amplifier is provided, which approximates gain control characteristics to approximate Linear-in-dB characteristics. A gain G is determined so as to have approximate Linear-in-dB characteristics passing through the maximum value, minimum value, and intermediate value of the gain by a capacitance ratio between capacitance of a higher order capacitor string composed of n capacitors or a lower order capacitor string composed of m capacitors selectively connected in parallel to an input fixed capacitor, and capacitance of a lower order capacitor string, a first correction capacitor string composed of n capacitors, or a second correction capacitor string composed of m capacitors selectively connected in parallel to a feedback loop fixed capacitor, in accordance with a gain control signal (Code) of lower order m bits and higher order n bits.

Abstract: Provided is a two-step parallel A/D converter capable of operating at a higher speed than in the prior art and easily performing correction of upper bit data. An upper limit voltage V.sub.H of a voltage range for lower bit conversion is amplified on the basis of a median voltage V.sub.M of the voltage range by a second differential amplifier, and the amplified voltage is set to a high level reference voltage SUB.sub.H for lower bit conversion. A lower limit voltage V.sub.L of the voltage range is amplified on the basis of the median voltage V.sub.M by a third differential amplifier, and the amplified voltage is set to a low level reference voltage SUB.sub.L for lower bit conversion. A voltage V.sub.IN of an input analog signal is amplified on the basis of the voltage V.sub.M by a first differential amplifier, and lower bit data is obtained from a position between the voltage SUB.sub.H and the voltage SUB.sub.L which is occupied by an obtained voltage SUB.sub.IN. The voltages SUB.sub.H and SUB.sub.