Patents by Inventor Shinichi Tanabe

Shinichi Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240086951
    Abstract: A satisfaction level calculation device (10) acquires environmental data detected by each of a plurality of environment sensors (20). The satisfaction level calculation device (10) sets each of a plurality of indexes about a space environment as a target index. The satisfaction level calculation device (10) calculates, from the environmental data acquired by measuring the target index, an individual satisfaction level, which is a satisfaction level of the target index. The satisfaction level calculation device (10) calculates, from the individual satisfaction level about each of the plurality of indexes, an overall satisfaction level, which is an overall satisfaction level about the space environment.
    Type: Application
    Filed: November 15, 2023
    Publication date: March 14, 2024
    Applicants: Mitsubishi Electric Corporation, WASEDA UNIVERSITY
    Inventors: Noriko TAKAHASHI, Kazuki HAMADA, Masanori HASHIMOTO, Yosuke KANEKO, Shinichi TANABE, Hiroaki NAGASHIMA
  • Publication number: 20230344396
    Abstract: The present technique pertains to a signal processing apparatus, a signal processing method, and a receiving apparatus that enable gain control to be appropriately performed on various interfering signals. An amplifier controls a gain according to a count value to amplify a signal, and a comparator compares the signal outputted by the amplifier with the count value. An accumulator counts the count value according to an output from the comparator. The present technique can be applied to, for example, a receiving apparatus that receives an RF signal for a television broadcast.
    Type: Application
    Filed: September 2, 2021
    Publication date: October 26, 2023
    Inventor: Shinichi Tanabe
  • Publication number: 20230010094
    Abstract: An in-vehicle system installed in a vehicle including a plurality of relay devices, wherein the plurality of relay devices are installed in a plurality of installation areas partitioned in the vehicle and include a plurality of connectors corresponding in number to the plurality of installation areas, the number and shapes of the plurality of connectors are standardized between the plurality of relay devices, harnesses extended from the plurality of installation areas are connected to the plurality of connectors either directly or via relay connectors, the plurality of relay devices include: a first relay device in which harnesses extended from different installation areas are connected to the plurality of connectors; and a second relay device other than the first relay device, and the number of relay connectors connected to the first relay device is no greater than the number of relay connectors connected to the second relay device.
    Type: Application
    Filed: November 24, 2020
    Publication date: January 12, 2023
    Inventors: Tsuyoshi KONTANI, Shinichi TANABE
  • Publication number: 20220220622
    Abstract: Techniques may relate to an electrode having high production efficiency of a synthetic gas containing at least CO. Such techniques relating to an electrode may include: a catalyst that produces at least carbon monoxide by a reduction reaction; an electrode material including the catalyst; and a solid base additive provided at least on the electrode material.
    Type: Application
    Filed: April 22, 2020
    Publication date: July 14, 2022
    Applicant: IDEMITSU KOSAN CO., LTD.
    Inventors: Qingxin JIA, Ichitaro WAKI, Shinichi TANABE
  • Patent number: 10176993
    Abstract: A third semiconductor layer (105) including a third nitride semiconductor is provided between an electrode (110) and a second semiconductor layer (104) including a second nitride semiconductor. The band gap of the second nitride semiconductor is set such that the carrier movement between a first semiconductor layer (103) and the third semiconductor layer (105) via the second semiconductor layer (104) is rate-determined by a diffusion process. The thickness of the second semiconductor layer (104) is set such that the carrier movement between the first semiconductor layer (103) and the third semiconductor layer (105) via the second semiconductor layer (104) is rate-determined by the diffusion process. The carrier movement between the first semiconductor layer (103) and the third semiconductor layer (105) via the second semiconductor layer (104) is rate-determined by a field emission process.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: January 8, 2019
    Assignee: NIPPON TELEGRAPH AND TELEPHONE CORPORATION
    Inventors: Dariush Zadeh, Shinichi Tanabe, Noriyuki Watanabe
  • Publication number: 20180130661
    Abstract: A third semiconductor layer (105) including a third nitride semiconductor is provided between an electrode (110) and a second semiconductor layer (104) including a second nitride semiconductor. The band gap of the second nitride semiconductor is set such that the carrier movement between a first semiconductor layer (103) and the third semiconductor layer (105) via the second semiconductor layer (104) is rate-determined by a diffusion process. The thickness of the second semiconductor layer (104) is set such that the carrier movement between the first semiconductor layer (103) and the third semiconductor layer (105) via the second semiconductor layer (104) is rate-determined by the diffusion process. The carrier movement between the first semiconductor layer (103) and the third semiconductor layer (105) via the second semiconductor layer (104) is rate-determined by a field emission process.
    Type: Application
    Filed: April 12, 2016
    Publication date: May 10, 2018
    Inventors: Dariush Zadeh, Shinichi Tanabe, Noriyuki Watanabe
  • Patent number: 8649459
    Abstract: A digital baseband signal for radio frequency transmission is processed prior to performing digital-to-analog conversion. The digital baseband signal is filtered. The number of bits of the digital baseband signal is reduced to minimise the size of the digital-to-analog converter. By performing some of the bit reduction before filtering, the size of the filter circuit is reduced whilst still meeting relevant performance parameters.
    Type: Grant
    Filed: April 14, 2009
    Date of Patent: February 11, 2014
    Assignee: Sony Corporation
    Inventors: Stuart Francis Glynn, Shinichi Tanabe
  • Patent number: 7750427
    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.
    Type: Grant
    Filed: January 6, 2009
    Date of Patent: July 6, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Kozo Watanabe, Shoji Yoshida, Masashi Sahara, Shinichi Tanabe, Takashi Hashimoto
  • Publication number: 20090152644
    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.
    Type: Application
    Filed: January 6, 2009
    Publication date: June 18, 2009
    Inventors: Kozo WATANABE, Shoji YOSHIDA, Masashi SAHARA, Shinichi TANABE, Takashi HASHIMOTO
  • Patent number: 7504297
    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.
    Type: Grant
    Filed: March 19, 2007
    Date of Patent: March 17, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Kozo Watanabe, Shoji Yoshida, Masashi Sahara, Shinichi Tanabe, Takashi Hashimoto
  • Patent number: 7397872
    Abstract: An automatic gain control circuit able to perform high speed and correct level acquisition, able to prevent occurrence of error, and able to prevent a crash of the system. An amplification gain controller outputs a gain control signal to an automatic gain control amplifier to amplify the received signal with maximum value when receiving a burst detection trigger signal. A second gain control signal based on the detected reception signal power is calculated when receiving a first burst synchronization detection signal; and this second gain control signal is output to the automatic gain control amplifier. A received digital signal is amplified with the second gain and integrated to find the reception signal power, from which a third gain control signal is calculated and outputted to the automatic gain control amplifier to amplify the received signal with this third gain.
    Type: Grant
    Filed: June 25, 2002
    Date of Patent: July 8, 2008
    Assignee: Sony Corporation
    Inventors: Kenji Komori, Masataka Wakamatsu, Hideaki Sato, Takashi Usui, Kazuyuki Saijo, Shinichi Tanabe, Hideo Morohashi, Kazuhiro Fujimura
  • Publication number: 20070246780
    Abstract: A technology is provided where a high performance Schottky-barrier diode and other semiconductor elements can be formed in the same chip controlling the increase in the number of steps. After a silicon oxide film is deposited over a substrate where an n-channel type MISFET is formed and the silicon oxide film over a gate electrode and n+ type semiconductor region is selectively removed, a Co film is deposited over the substrate and a CoSi2 layer is formed over the n+ type semiconductor region and the gate electrode by applying a heat treatment to the substrate.
    Type: Application
    Filed: March 19, 2007
    Publication date: October 25, 2007
    Inventors: Kozo Watanabe, Shoji Yoshida, Masashi Sahara, Shinichi Tanabe, Takashi Hashimoto
  • Patent number: 7206728
    Abstract: A step of preparing data of (1) material properties of a first part and so on and data of (2) an amount of solar radiation passing through the translucent member to reach a measuring device having a shape imitating a human body part, an amount of solar radiation to the structure, an amount of convection heat transfer in the structure, an amount of radiation heat transfer in the structure, humidity in the structure and/or a thermo-regulating function of the measuring device, and calculating at least one of the amount of heat loss from the surface of the measuring device, the temperature of the measuring device and/or the wettedness at the surface of the measuring device based on at least one in each of data (1) and (2), and a step (b) of calculating a thermal comfort index of the measuring device by using a result of the above calculation, are presented, whereby the thermal comfort of a structure is evaluated without using a laboratory equipment.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: April 17, 2007
    Assignee: Asahi Glass Company, Limited
    Inventors: Yoshiichi Ozeki, Toru Takabayashi, Shinichi Tanabe
  • Patent number: 7042292
    Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage so as to compensate the linearity of the variable gain circuit to the extent of the external control voltage where the variable gain circuit loses linearity. This gain control circuit is applied to an AGC circuit of the transmitting stage in a CDMA-type mobile phone.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: May 9, 2006
    Assignee: Sony Corporation
    Inventors: Hideo Morohashi, Shinichi Tanabe
  • Patent number: 7015758
    Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage so as to compensate the linearity of the variable gain circuit to the extent of the external control voltage where the variable gain circuit loses linearity. This gain control circuit is applied to an AGC circuit of the transmitting stage in a CDMA-type mobile phone.
    Type: Grant
    Filed: February 28, 2005
    Date of Patent: March 21, 2006
    Assignee: Sony Corporation
    Inventors: Hideo Morohashi, Shinichi Tanabe
  • Publication number: 20050170804
    Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage so as to compensate the linearity of the variable gain circuit to the extent of the external control voltage where the variable gain circuit loses linearity. This gain control circuit is applied to an AGC circuit of the transmitting stage in a CDMA-type mobile phone.
    Type: Application
    Filed: February 28, 2005
    Publication date: August 4, 2005
    Inventors: Hideo Morohashi, Shinichi Tanabe
  • Publication number: 20050143033
    Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage so as to compensate the linearity of the variable gain circuit to the extent of the external control voltage where the variable gain circuit loses linearity. This gain control circuit is applied to an AGC circuit of the transmitting stage in a CDMA-type mobile phone.
    Type: Application
    Filed: February 28, 2005
    Publication date: June 30, 2005
    Inventors: Hideo Morohashi, Shinichi Tanabe
  • Patent number: 6891405
    Abstract: The present invention provides systems and methods related to a variable gain amplifier. The variable gain amplifier includes a first differential amplifier, a second differential amplifier, a combining circuit, and a current control circuit. The first differential amplifier circuit and the second differential amplifier circuit share a common input signal and have different amplification degrees. Each of the first and second differential amplifier circuits includes a first transistor and a second transistor that form a differential pair. The first transistor and the second transistor of each differential amplifier circuit have bases that are supplied with the input signal, and collectors that output signals to the combining circuit. The current control circuit changes a ratio between a bias current of the first differential amplifier circuit and a bias current of said second differential amplifier circuit based on a gain control signal.
    Type: Grant
    Filed: July 10, 2002
    Date of Patent: May 10, 2005
    Assignee: Sony Corporation
    Inventors: Kazuhiro Fujimura, Shinichi Tanabe
  • Patent number: 6876257
    Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage so as to compensate the linearity of the variable gain circuit to the extent of the external control voltage where the variable gain circuit loses linearity. This gain control circuit is applied to an AGC circuit of the transmitting stage in a CDMA-type mobile phone.
    Type: Grant
    Filed: January 16, 2001
    Date of Patent: April 5, 2005
    Assignee: Sony Corporation
    Inventors: Hideo Morohashi, Shinichi Tanabe
  • Publication number: 20040133406
    Abstract: A step of preparing data of (1) material properties of a first part and so on and data of (2) an amount of solar radiation passing through the translucent member to reach a measuring device having a shape imitating a human body part, an amount of solar radiation to the structure, an amount of convection heat transfer in the structure, an amount of radiation heat transfer in the structure, humidity in the structure and/or a thermo-regulating function of the measuring device, and calculating at least one of the amount of heat loss from the surface of the measuring device, the temperature of the measuring device and/or the wettedness at the surface of the measuring device based on at least one in each of data (1) and (2), and a step (b) of calculating a thermal comfort index of the measuring device by using a result of the above calculation, are presented, whereby the thermal comfort of a structure is evaluated without using a laboratory equipment.
    Type: Application
    Filed: September 25, 2003
    Publication date: July 8, 2004
    Applicant: Asahi Glass Company, Limited
    Inventors: Yoshiichi Ozeki, Toru Takabayashi, Shinichi Tanabe