Patents by Inventor Shinichi Tanabe

Shinichi Tanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040037378
    Abstract: An automatic gain control circuit able to perform high speed and correct level acquisition, able to prevent occurrence of error, and able to prevent a crash of the system, a method of same, and a demodulation apparatus, provided with an amplification gain controller 211 for outputting a gain control signal to an automatic gain control amplifier 201 so as to amplify the reception signal with the maximum value when receiving a burst detection starting use trigger signal, calculating a second gain based on a reception signal power value detected at a reception signal power monitor 202 when receiving a first burst synchronization detection signal from the burst detector, outputting the gain control signal to the automatic gain control amplifier 201 so as to amplify the reception signal with the second gain, receiving the digital reception signal amplified with the second gain and integrating the same to find the reception signal power value, calculating a third gain based on the found reception signal power value
    Type: Application
    Filed: August 4, 2003
    Publication date: February 26, 2004
    Inventors: Kenji Komori, Masataka Wakamatsu, Hideaki Sato, Takashi Usui, Kazuyuki Saijo, Shinichi Tanabe, Hideo Morohashi, Kazuhiro Fujimura
  • Publication number: 20030034841
    Abstract: A variable gain amplifier is provided with a first differential amplifier circuit and a second differential amplifier circuit each formed with transistors. A common signal is inputted to each of the differential amplifier circuits, and output signals of the differential amplifier circuits are added together for output via resistances. When a voltage of a variable voltage source is increased, a bias current of the first differential amplifier circuit having a high gain is increased, and therefore the gain of the first differential amplifier circuit is raised, resulting in an increase in overall gain. When the voltage of the variable voltage source is decreased, a bias current of the second differential amplifier circuit having a low gain is increased and therefore the gain of the second differential amplifier circuit is raised, so that the second differential amplifier circuit has greater effect and thus provides an amplifier circuit with a high saturation input level.
    Type: Application
    Filed: July 10, 2002
    Publication date: February 20, 2003
    Inventors: Kazuhiro Fujimura, Shinichi Tanabe
  • Patent number: 6517213
    Abstract: An indicator device is intended to make an indication by illuminating a predetermined indicating surface, and comprises a light source (12) for emitting a light (L1) of the first wavelength and a fluorescent plate (22) disposed between the light source and the indicating surface for changing at least part of the light of the first wavelength projected from the light source into a light (L2) of the second wavelength longer than the first wavelength and projecting it towards the indicating surface.
    Type: Grant
    Filed: November 25, 1998
    Date of Patent: February 11, 2003
    Assignee: IDEC Izumi Corporation
    Inventors: Toshihiro Fujita, Akito Okamoto, Masaru Mamiya, Ikkan Nishihara, Shinichi Tanabe
  • Patent number: 6445055
    Abstract: A circuit region 2 on a main surface of an SOI substrate, and a isolating region 9b defined by insulating isolation trenches 4a and 4b are connected by a wiring resistor, or a diffused resistor 11a in the SOI substrate. The isolating region 9b and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11b in the SOI substrate. Furthermore, a circuit region 3 on a main surface of an SOI substrate, and a isolating region 9c defined by insulating isolation trenches 4c and 4d are connected by a wiring resistor, or a diffused resistor 11d in the SOI substrate. The isolating region 9c and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11c in the SOI substrate. As a result, distribution of voltage applied between the circuit regions 2 and 3 by the wiring resistors or the diffused resistors 11a to 11d can increase the withstand voltage of a semiconductor integrated circuit.
    Type: Grant
    Filed: August 9, 2001
    Date of Patent: September 3, 2002
    Assignees: Hitachi, Ltd., Hitachi ULSI Systems Co., Ltd.
    Inventors: Takayuki Iwasakii, Yusuke Takeuchi, Yoshiaki Yuyama, Shinichi Tanabe, Koki Sakai, Minehiro Nemoto, Seigo Yukutake, Yasuyuki Kojima, Atsuo Watanabe, Mitsuaki Horiuchi
  • Patent number: 6388529
    Abstract: A grounded emitter amplifier and a radio communication device using the same in which a bias voltage is generated in order to adjust an emitter current of a transistor in a grounded emitter amplification circuit so that the emitter current does not receive an influence of variations in several parameters of the transistor such as a current amplification factor hfe.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: May 14, 2002
    Assignee: Sony Corporation
    Inventors: Hideo Morohashi, Shinichi Tanabe
  • Publication number: 20020017686
    Abstract: A circuit region 2 on a main surface of an SOI substrate, and a isolating region 9b defined by insulating isolation trenches 4a and 4b are connected by a wiring resistor, or a diffused resistor 11a in the SOI substrate. The isolating region 9b and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11b in the SOI substrate. Furthermore, a circuit region 3 on a main surface of an SOI substrate, and a isolating region 9c defined by insulating isolation trenches 4c and 4d are connected by a wiring resistor, or a diffused resistor lid in the SOI substrate. The isolating region 9c and an intermediate region 9 are connected by a wiring resistor, or a diffused resistor 11c in the SOI substrate. As a result, distribution of voltage applied between the circuit regions 2 and 3 by the wiring resistors or the diffused resistors 1a to 11d can increase the withstand voltage of a semiconductor integrated circuit.
    Type: Application
    Filed: August 9, 2001
    Publication date: February 14, 2002
    Inventors: Takayuki Iwasakii, Yusuke Takeuchi, Yoshiaki Yuyama, Shinichi Tanabe, Koki Sakai, Minehiro Nemoto, Seigo Yukutake, Yasuyuki Kojima, Atsuo Watanabe, Mitsuaki Horiuchi
  • Publication number: 20010013811
    Abstract: A grounded emitter amplifier and a radio communication device using the same in which a bias voltage is generated in order to adjust an emitter current of a transistor in a grounded emitter amplification circuit so that the emitter current does not receive an influence of variations in several parameters of the transistor such as a current amplification factor hfe.
    Type: Application
    Filed: January 12, 2001
    Publication date: August 16, 2001
    Applicant: Sony Corporation
    Inventors: Hideo Morohashi, Shinichi Tanabe
  • Publication number: 20010008836
    Abstract: A gain control circuit comprises a variable gain circuit having a predetermined gain control range and a control voltage supply circuit for supplying an internal control voltage to the variable gain circuit as a gain control signal. In this gain control circuit, the control voltage supply circuit generates the internal control voltage in response to an external control voltage as to compensate a linearity of the variable gain circuit to an extent of the external control voltage where the variable gain circuit loses a linearity. This gain control circuit is applied to an AGC circuit of a transmitting stage in a CDMA type mobile phone.
    Type: Application
    Filed: January 16, 2001
    Publication date: July 19, 2001
    Applicant: Sony Corporation
    Inventors: Hideo Morohashi, Shinichi Tanabe
  • Patent number: 5936955
    Abstract: A data communication system for a computer system in which a plurality of computers are mutually connected includes: a plurality of computers each having an area to store a command to execute a data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the plurality of computers; and a transmission permitting component, connected between the switch circuit and one of the plurality of computers, for outputting a signal to permit the data transmission from such one computer to such another computer; a communication component for transmitting the data received from such one computer by outputting the transmission permission signal from the transmission permitting component to such another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from such one computer to such another computer; and a communication control component to abandon the data that is subsequently recei
    Type: Grant
    Filed: November 5, 1997
    Date of Patent: August 10, 1999
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Aimoto, Hidenori Inouchi, Shoichi Murase, Shinichi Tanabe, Kazuhiro Hashimoto, Hiroshi Iwamoto, Hiroshi Ohguro, Takehisa Hayashi, Haruyuki Nakayama, Kenji Nakajima, Satoshi Yoshizawa, Hideki Murayama
  • Patent number: 5835492
    Abstract: A data communication system for a computer system in which computers are mutually connected includes: each computer having an area to store a command to execute data communication on the basis of it and a buffer area to store data; a switch circuit to mutually selectively connect the computers; and a transmission permitting component, connected between the switch circuit and one of the computers, for outputting a signal to permit the data transmission from one computer to another computer; a communication component for transmitting the data received from one computer by outputting the transmission permission signal from the transmission permitting component to another computer through the switch circuit; a detecting component to detect the occurrence of an abnormality regarding the data communication from one computer to another computer; and a communication control component to abandon the data that is subsequently received from one computer by outputting the transmission permission signal in accordance with
    Type: Grant
    Filed: September 18, 1995
    Date of Patent: November 10, 1998
    Assignee: Hitachi, Ltd.
    Inventors: Takeshi Aimoto, Hidenori Inouchi, Shoichi Murase, Shinichi Tanabe, Kazuhiro Hashimoto, Hiroshi Iwamoto, Hiroshi Ohguro, Takehisa Hayashi, Haruyuki Nakayama, Kenji Nakajima, Satoshi Yoshizawa, Hideki Murayama
  • Patent number: 5079525
    Abstract: An RF modulator comprising an FM modulator supplied with an audio signal, and AM modulator supplied with the FM modulator output and a video signal, an oscillator for generating a sound subcarrier signal, and an oscillator for generating a main carrier signal. Each of the oscillators consists of a VCO with a PLL circuit, and the entire components are composed of a single IC chip so as to be formed into a compact miniature structure. A modified RF modulator includes a PLL circuit for varying the oscillation frequency of a VCO by a variable frequency divider, and a modulation circuit supplied with a modulating signal and the oscillation output of the VCO. The division ratio (integer) of the variable frequency divider is continuously varied, and the reference frequency of a reference oscillator is set to be less than a predetermined channel interval frequency, thereby reducing the frequency error in the modulated signal output.
    Type: Grant
    Filed: December 6, 1990
    Date of Patent: January 7, 1992
    Assignee: Sony Corporation
    Inventors: Nobuyuki Ishikawa, Hiroshi Higuchi, Hisaaki Narahara, Shinichi Tanabe, Fumio Ishikawa