Patents by Inventor Shinichi Watanuki

Shinichi Watanuki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10921515
    Abstract: A semiconductor device includes a substrate having a first surface and a second surface that have top and back relation, an insulating layer formed on the first surface of the substrate, and an optical waveguide formed on the insulating layer and formed of a semiconducting layer. A first opening is formed on the second surface of the substrate. The first opening overlaps the optical waveguide in plan view.
    Type: Grant
    Filed: November 12, 2019
    Date of Patent: February 16, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Shinichi Watanuki, Tohru Kawai
  • Patent number: 10895681
    Abstract: The semiconductor device has an optical waveguide formed on a substrate, a first conductor film formed in the same layer as the optical waveguide, an insulating film formed on the first conductor film, a second conductor film formed on the insulating film, and a first interlayer insulating film formed on the substrate so as to cover the optical waveguide and the second conductor film. The semiconductor device includes a first contact hole reaching the first conductor film, a second contact hole reaching the second conductor film, a first contact plug formed in the first contact hole, and a second contact plug formed in the second contact hole. The first conductor film is disposed between the first contact plugs and the board, but the second conductor film is not disposed between the first contact plugs and the board.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: January 19, 2021
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Shinichi Watanuki, Yasutaka Nakashiba
  • Patent number: 10818813
    Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 27, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tomoo Nakayama, Shinichi Watanuki, Futoshi Komatsu, Teruhiro Kuwajima, Takashi Ogura, Hiroyuki Okuaki, Shigeaki Shimizu
  • Publication number: 20200192039
    Abstract: A semiconductor device includes a substrate having a first surface and a second surface that have top and back relation, an insulating layer formed on the first surface of the substrate, and an optical waveguide formed on the insulating layer and formed of a semiconducting layer. A first opening is formed on the second surface of the substrate. The first opening overlaps the optical waveguide in plan view.
    Type: Application
    Filed: November 12, 2019
    Publication date: June 18, 2020
    Inventors: Yasutaka NAKASHIBA, Shinichi WATANUKI, Tohru KAWAI
  • Patent number: 10578805
    Abstract: An optical waveguide formed at the same layer as that of a microscopic optical device and a spot size converter largely different in size are integrally formed. A semiconductor device has an optical waveguide part functioning as a spot size converter. The optical waveguide part includes a plurality of optical waveguide bodies penetrating through an interlayer insulation layer in the thickness direction.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: March 3, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Shinichi Watanuki
  • Patent number: 10553734
    Abstract: An improvement is achieved in the reliability of a semiconductor device. Over an insulating layer, an optical waveguide and a p-type semiconductor portion are formed. Over the p-type semiconductor portion, a multi-layer body including an n-type semiconductor portion and a cap layer is formed. Over a first interlayer insulating film covering the optical waveguide, the p-type semiconductor portion, and the multi-layer body, a heater located over the optical waveguide is formed. In the first interlayer insulating film, first and second contact holes are formed. A first contact portion electrically coupled with the p-type semiconductor portion is formed continuously in the first contact hole and over the first interlayer insulating film. A second contact portion electrically coupled with the cap layer is formed continuously in the second contact hole and over the first interlayer insulating film.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: February 4, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Teruhiro Kuwajima, Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama
  • Patent number: 10527872
    Abstract: A low reflectance film with a second reflectance (50% or lower) lower than a first reflectance is formed between an optical directional coupler and a first-layer wiring with the first reflectance. Thus, even when the first-layer wiring is formed above the optical directional coupler, the influence of the light reflected by the first-layer wiring on the optical signal propagating through the first optical waveguide and the second optical waveguide of the optical directional coupler can be reduced. Accordingly, the first-layer wiring can be arranged above the optical directional coupler, and the restriction on the layout of the first-layer wiring is relaxed.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: January 7, 2020
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki
  • Publication number: 20190391327
    Abstract: The semiconductor device has an optical waveguide formed on a substrate, a first conductor film formed in the same layer as the optical waveguide, an insulating film formed on the first conductor film, a second conductor film formed on the insulating film, and a first interlayer insulating film formed on the substrate so as to cover the optical waveguide and the second conductor film. The semiconductor device includes a first contact hole reaching the first conductor film, a second contact hole reaching the second conductor film, a first contact plug formed in the first contact hole, and a second contact plug formed in the second contact hole. The first conductor film is disposed between the first contact plugs and the board, but the second conductor film is not disposed between the first contact plugs and the board.
    Type: Application
    Filed: May 14, 2019
    Publication date: December 26, 2019
    Inventors: Shinichi WATANUKI, Yasutaka NAKASHIBA
  • Patent number: 10466415
    Abstract: A semiconductor device including an optical waveguide and a p-type semiconductor portion is configured as follows. The optical waveguide includes: a first semiconductor layer formed on an insulating layer; an insulating layer formed on the first semiconductor layer; and a second semiconductor layer formed on the insulating layer. The p-type semiconductor portion includes the first semiconductor layer. The film thickness of the p-type semiconductor portion is smaller than that of the optical waveguide. By forming the insulating layer between the first semiconductor layer and the second semiconductor layer, control of the film thicknesses of the optical waveguide and the p-type semiconductor portion is facilitated. Specifically, when the unnecessary second semiconductor layer is removed by etching in a step of forming the p-type semiconductor portion, the insulating layer which is the lower layer functions as an etching stopper, and the film thickness of the p-type semiconductor portion can be easily adjusted.
    Type: Grant
    Filed: April 24, 2018
    Date of Patent: November 5, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Yasutaka Nakashiba, Shinichi Watanuki
  • Patent number: 10416382
    Abstract: In an optical waveguide section of an SIS type having a configuration of stacking a second semiconductor layer over a first semiconductor layer with a dielectric layer interposed, the first semiconductor layer is electrically coupled to a first electrode at a first lead-out section where the second semiconductor layer is not stacked. Further, the second semiconductor layer is electrically coupled to a second electrode at a second lead-out section not overlapping with the first semiconductor layer. As a result, when a contact hole for forming the second electrode is formed by dry etching, the dielectric layer between the first semiconductor layer and the second semiconductor layer is not damaged or broken and hence short-circuit failure between the first semiconductor layer and the second semiconductor layer can be prevented. The reliability of the optical waveguide section therefore can be improved.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasutaka Nakashiba, Shinichi Watanuki
  • Patent number: 10416481
    Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: September 17, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Tohru Kawai, Shinichi Watanuki, Yasutaka Nakashiba
  • Patent number: 10355161
    Abstract: To achieve a high-reliability germanium photoreceiver. A photoreceiver portion of a germanium photoreceiver comprised of a p type silicon core layer, an i type germanium layer, and an n type silicon layer is covered with a second insulating film and from a coupling hole formed in the second insulating film, a portion of the upper surface of the photoreceiver portion is exposed. The coupling hole has, on the inner wall thereof, a barrier metal film and the barrier metal film has thereon a first-layer wiring made of a tungsten film. Tungsten hardly diffuses from the tungsten film into the i type germanium layer even when a thermal stress is applied, making it possible to prevent the resulting germanium photoreceiver from having diode characteristics deteriorated by the thermal stress.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: July 16, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Teruhiro Kuwajima, Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama
  • Publication number: 20190198703
    Abstract: In order to improve the performance of a semiconductor device, a semiconductor layer EP is formed over a p-type semiconductor PR. An n-type semiconductor layer NR1 is formed over the semiconductor layer EP. The semiconductor layer PR, the semiconductor layer EP, and the semiconductor layer NR1 respectively configure part of a photoreceiver. A cap layer of a material different from that of the semiconductor layer EP is formed over the semiconductor layer EP, and a silicide layer, which is a reaction product of a metal and the material included in the cap layer, is formed within the cap layer. A plug having a barrier metal film BM1 is formed over the cap layer through the silicide layer. Here, a reaction product of the metal and the material included in the semiconductor layer NR1 is not formed within the semiconductor layer NR1.
    Type: Application
    Filed: November 13, 2018
    Publication date: June 27, 2019
    Inventors: Tomoo NAKAYAMA, Shinichi WATANUKI, Futoshi KOMATSU, Teruhiro KUWAJIMA, Takashi OGURA, Hiroyuki OKUAKI, Shigeaki SHIMIZU
  • Publication number: 20190196110
    Abstract: An optical waveguide formed at the same layer as that of a microscopic optical device and a spot size converter largely different in size are integrally formed. A semiconductor device has an optical waveguide part functioning as a spot size converter. The optical waveguide part includes a plurality of optical waveguide bodies penetrating through an interlayer insulation layer in the thickness direction.
    Type: Application
    Filed: November 7, 2018
    Publication date: June 27, 2019
    Inventors: Yasutaka NAKASHIBA, Shinichi WATANUKI
  • Publication number: 20190196099
    Abstract: Two optical waveguides and an insulating film provided to cover the optical waveguides are formed over an insulating layer. Two wirings and a heater metal wire are formed over the insulating film via an insulating film different from the above insulating film. The latter insulating film is thinner than the former insulating film, and has a higher refractive index than the former insulating film. The leaked light from either of the two optical waveguides can be suppressed or prevented from being reflected by any one of the two wirings, the heater metal wire, and the like to travel again toward the two optical waveguides by utilizing the difference between the refractive indices of the two insulating films.
    Type: Application
    Filed: November 7, 2018
    Publication date: June 27, 2019
    Inventors: Shinichi WATANUKI, Yasutaka NAKASHIBA
  • Publication number: 20190196231
    Abstract: The performances of a semiconductor device are improved. The semiconductor device includes an insulation layer, an optical waveguide part formed over the insulation layer, and including a p type semiconductor region and an n type semiconductor region formed therein, and an interlayer insulation film formed over the insulation layer in such a manner as to cover the optical waveguide part. At the first portion of the optical waveguide part, in a cross sectional view perpendicular to the direction of extension of the optical waveguide part, the n type semiconductor region is arranged at the central part of the optical waveguide part, and the p type semiconductor region is arranged in such a manner as to surround the entire circumference of the n type semiconductor region.
    Type: Application
    Filed: November 6, 2018
    Publication date: June 27, 2019
    Inventors: Tohru KAWAI, Shinichi WATANUKI, Yasutaka NAKASHIBA
  • Publication number: 20190187370
    Abstract: In an optical waveguide section of an SIS type having a configuration of stacking a second semiconductor layer over a first semiconductor layer with a dielectric layer interposed, the first semiconductor layer is electrically coupled to a first electrode at a first lead-out section where the second semiconductor layer is not stacked. Further, the second semiconductor layer is electrically coupled to a second electrode at a second lead-out section not overlapping with the first semiconductor layer. As a result, when a contact hole for forming the second electrode is formed by dry etching, the dielectric layer between the first semiconductor layer and the second semiconductor layer is not damaged or broken and hence short-circuit failure between the first semiconductor layer and the second semiconductor layer can be prevented. The reliability of the optical waveguide section therefore can be improved.
    Type: Application
    Filed: October 31, 2018
    Publication date: June 20, 2019
    Inventors: Yasutaka NAKASHIBA, Shinichi WATANUKI
  • Patent number: 10317769
    Abstract: In a semiconductor device connected to a first optical waveguide, a phase modulation unit, and a second optical waveguide in this order and having an optical modulator guiding light in a first direction, the phase modulation unit includes: a semiconductor layer whose length in the first direction is larger than a width in a second direction orthogonal to the first direction and which is made of monocrystalline silicon; a core part serving as an optical waveguide region formed on the semiconductor layer, and extending in the first direction; a pair of slab parts arranged on both sides of the core part in the second direction; a first electrode coupled with one of the slab parts; and a second electrode coupled with the other of the slab parts. The core part has a p type semiconductor region and an n type semiconductor region extending in the first direction, and the second direction coincides with a crystal orientation <100> of the semiconductor layer.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: June 11, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Watanuki, Yasutaka Nakashiba, Masaru Wakabayashi
  • Patent number: 10295743
    Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.
    Type: Grant
    Filed: August 17, 2015
    Date of Patent: May 21, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiroyuki Kunishima, Yasutaka Nakashiba, Masaru Wakabayashi, Shinichi Watanuki, Ken Ozawa, Tatsuya Usami, Yoshiaki Yamamoto, Keiji Sakamoto
  • Patent number: 10211352
    Abstract: Germanium (Ge) contamination to a semiconductor manufacturing apparatus is suppressed. Germanium is a dissimilar material in a silicon semiconductor process. A semiconductor device is provided with a Ge photodiode including an n-type germanium layer, and a plug capacitively coupled to the n-type germanium layer. In other words, the n-type germanium layer of the Ge photodiode and the plug are not in direct contact with each other but are capacitively coupled to each other.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 19, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Shinichi Watanuki, Futoshi Komatsu, Tomoo Nakayama, Takashi Ogura, Teruhiro Kuwajima