Abstract: A semiconductor memory device, in which a burst operation is performed using a memory core, has a read/write trigger signal generating circuit and a read/write signal generating circuit. The read/write trigger signal generating circuit generates a read/write signal request from a predetermined timing signal during the burst operation. The read/write signal generating circuit receives an output signal from the read/write trigger signal generating circuit and outputs a read/write signal after a core operation just prior to receipt of the output signal is complete and the subsequent activation of a row side is complete.

Abstract: A road map management system is provided as follows: drawing a past-direction distribution map (Image A) and a future-direction distribution map (Image B) using multiple vehicles' traveling position data collected via a wide area network during a past-direction data collection period and a future-direction data collection period, respectively; comparing the two distribution maps to extract a differential distribution; defining under a predetermined condition as a recently opened or closed road the differential distribution, which is absent from Image A and present in Image B, or present in Image A and absent from Image B, respectively; and reflecting the defined results on the existing road map data to update.

Abstract: An information processing apparatus, processing method therefore, and program allowing computer to execute same are provided.

Abstract: An optical disc unit 2001 comprises: reflective surface detection means 1010 for detecting a reflective surface; focus control means (1202, 1003, 1009, 1008, 1003, 1012, 1005 and 1204) for performing focus control to a reflective surface so that the distance between the focal point of an optical beam applied to an optical disc 2100 and the reflective surface is within a predetermined error limit; shift means 1007 for shifting the focal point of the optical beam in a direction perpendicular to the optical disc; and control means 1006 for controlling the focus control means and the shift means.

Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

Abstract: A semiconductor memory device with low power consumption in driving control signals of shift registers. The device contains a plurality of memory cell arrays each composed of a predetermined number of rows of memory cells. One set of shift registers are coupled to each cell array, and the nth set of shift registers successively activate word line selection signals according to a given control signal, so that the corresponding word lines of the nth cell array will be refreshed. Also coupled to each cell array is a shift register controller. The nth shift register controller provides a control signal to the nth set of shift registers when the nth cell array is being refreshed. When the refresh of that cell array is finished, the nth shift register controller forwards the control signal to the (n+1)th set of shift registers, thus initiating refresh operation for the (n+1)th cell array.

Abstract: An axial gap electronic motor includes a stator having a plurality of poles, and a rotor. Each pole is formed of a stator iron core made of a magnet body and a coil wound therearound. The rotor has a plurality of poles formed of permanent magnet and arranged along a rotation axis direction of said rotor with a predetermined gap provided therebetween. The stator has a magnetic force generating section in which a plurality of the stator iron cores is arranged in a ring shape on a concentric circle with the rotation axis line of the rotor being a center axis. Each of teeth of the stator iron core is provided with a skew.

Abstract: An optical disk apparatus includes an optical detector which has light receiving areas divided nearly concentrically with an optical beam and outputs a signal corresponding to the amount of the reflected light from an optical disk. A surface vicinity detecting section adds up signals from all the light-receiving areas of the optical detector and outputs a detection signal. The detection signal continuously varies so as to have one maximum level while a beam spot of the optical beam moves from the surface of the information medium to the information plane. An information plane detecting section judges that the focus or the beam spot of the optical beam comes closer to the information plane of the optical disk by detecting the gradient of the detection signal. An approach of a condensing lens and the optical disk is judged based on the judgment results, and thus a collision of the condensing lens and the optical disk can be prevented.

Abstract: A register part of a mode register has a plurality of operation setting parts in which plural types of operating specifications are respectively set to operate the semiconductor memory. The mode register outputs a soft reset signal when at least a value of one-bit of the register part represents a reset state. A reset signal generator outputs a reset signal for resetting an internal circuit in response to the soft reset signal. In the present invention, a system that controls the semiconductor memory is required to necessarily assign a predetermined bit with a setting command of the mode register in order to generate the soft reset signal. Accordingly, it is possible to reliably reset the internal circuit by external control.

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A method for controlling a semiconductor memory in which a mode register can be set in a burst mode. To set an operation mode in the burst mode, the semiconductor memory is changed first from the burst mode, through a power-down mode, to a standby mode of non-burst mode. Then the semiconductor memory is changed to a mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Abstract: An optical disc apparatus comprises: rotating means for rotating an information recording medium; a light source for irradiating a light beam onto a data side of the information recording medium; converging means for converging said light beam; focus error detecting means for detecting a difference between said data side and the focus of the light beam converged by said converging means; focus direction transferring means for transferring said converging means in a direction perpendicular to said data side; focus controlling means for driving said focus direction transferring means based on the output of said focus error detecting means in such a way that said light beam converges on said data side in a predetermined state; tracking direction transferring means for transferring said light source in the radius direction of said information recording medium; and tilt calculating means for calculating average values of the outputs of said focus controlling means obtained for a period of time, which is an integer

Abstract: A semiconductor device includes a word line drive circuit for resetting the word line by driving the word line connected to a memory cell and is constituted so as to switch a reset level of the word line drive circuit, which is set at the time of the reset operation of the word line, between a first potential such as a ground potential and a second potential such as a negative potential. Further, a semiconductor device including a memory cell array formed by arranging a plurality of memory cells and a word line reset level generating circuit for generating a negative potential makes it possible to vary the amount of a current supply of the word line reset level generating circuit when non-selected word lines are set to a negative potential by applying the output of the word line reset level generating circuit to the non-selected word lines, and varies the amount of the current supply of the negative potential in accordance with the operation of the memory cell array.

Abstract: A steering damper in a motorcycle includes a vane partitioning a chamber in a damper housing into two oil chambers, wherein hydraulic fluid flows between the two chambers to generate attenuating force. The steering damper also includes a damper shaft connected to the vane and supporting the vane for rocking motion with respect to the housing, and a hydraulic pressure control valve. The housing is attached to a head pipe, and the damper shaft is attached to a steering system. When the head pipe is to be attached to the housing, the housing is extended rearwardly behind a top bridge, and a linear solenoid for driving and controlling the hydraulic pressure control valve is attached to the housing and disposed below the extension thereof.

Abstract: First dummy memory cells connected to a first dummy signal line have the same shape and characteristics as those of a real memory cell. The first dummy memory cells are arranged to be adjacent to outermost real memory cells. A voltage setting circuit changes the voltage of the first dummy signal line from a first voltage to a second voltage in order to write test data onto the first dummy memory cell during a test mode. By writing data of a logic opposite to that of the test data onto the real memory cell adjacent to the first dummy memory cell by means of an operation control circuit, a leak failure that may occur between the first dummy memory cell and the real memory cell adjacent thereto can be checked.

Abstract: A semiconductor memory device, in which a burst operation is performed using a memory core, has a read/write trigger signal generating circuit and a read/write signal generating circuit. The read/write trigger signal generating circuit generates a read/write signal request from a predetermined timing signal during the burst operation. The read/write signal generating circuit receives an output signal from the read/write trigger signal generating circuit and outputs a read/write signal after a core operation just prior to receipt of the output signal is complete and the subsequent activation of a row side is complete.

Abstract: There is provided an axial gap electronic motor capable of decreasing cogging torque and thus decreasing vibrations and noise. A stator of the motor has a magnetic force generating section 21 in which a plurality of stator iron cores 24 are arranged in a ring shape, and teeth 25 of each of the stator iron cores 24 are provided with a skew 26 inclined through a predetermined angle with respect to the radial direction of the rotors 31, 32.

Abstract: A method for controlling a semiconductor memory in which mode register can be set in burst mode. To set an operation mode in burst mode, the semiconductor memory is changed first from the burst mode, through power-down mode, to standby mode of non-burst mode. Then the semiconductor memory is changed to mode register set mode to set the mode register when commands are input in the same predetermined sequence that is used in the non-burst mode.

Abstract: A semiconductor memory device includes a plurality of bit line pairs, each of which includes a first bit line and a second bit line, a plurality of memory cells which are coupled to said first bit line, and store electric charge in capacitors, a dummy cell which is coupled to a second bit line, and is charged with a predetermined potential, a sense amplifier which amplifies a potential difference between the first bit line and the second bit line, and a control circuit which charges said dummy cell with the predetermined potential only for a fixed time period.

Abstract: An inexpensive switch connecting structure is provided capable of avoiding abnormal wear-off or deformation of a contact spring of a supporting plate even if a movement in a basic shape is placed in a timepiece case having a shape different from the movement and a push button is repeatedly used. The switch connecting structure includes a supporting plate attached to cap a movement of a timepiece and provided with a contact spring having a contact portion at a tip brought into contact with a switch contact portion of a circuit board, and a switch regulating plate provided with a switch spring on an outer periphery corresponding to said contact spring and covering at least part of said supporting plate, wherein said switch spring is flexed by operation of an externally operated component attached to a timepiece case, thereby bringing the contact portion of the contact spring of said supporting plate into contact with the switch contact portion of said circuit board.