Patents by Inventor Shinichiro Mitani
Shinichiro Mitani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7049680Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: GrantFiled: October 25, 2004Date of Patent: May 23, 2006Assignee: Renesas Technology Corp.Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Patent number: 7023071Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: GrantFiled: June 15, 2004Date of Patent: April 4, 2006Assignees: Hitachi Ulsi Engineering Corp., Renesas Technology Corp.Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Patent number: 7022568Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: GrantFiled: October 12, 2004Date of Patent: April 4, 2006Assignees: Renesas Technology Corp., Hitachi ULSI Engineering Corp.Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Patent number: 6933564Abstract: An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel type MISFET is to be formed, vertically with respect to a main surface of a semiconductor to form a first p-type pocket layer. Subsequently, an impurity of a p conduction type is implanted into a region between the n-type diffusion region and the first p-type pocket layer obliquely relative to the main surface of the semiconductor substrate to form a second p-type pocket layer. In this arrangement, the concentration of the impurity ion forming the second p-type pocket layer is made higher than the concentration of the impurity ion used to form the first p-type pocket layer.Type: GrantFiled: January 28, 2003Date of Patent: August 23, 2005Assignee: Renesas Technology Corp.Inventors: Youhei Yanagida, Katsuhiko Ichinose, Tomohiro Saito, Shinichiro Mitani
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Publication number: 20050082622Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: ApplicationFiled: October 25, 2004Publication date: April 21, 2005Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Publication number: 20050062077Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: ApplicationFiled: October 12, 2004Publication date: March 24, 2005Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Publication number: 20040264274Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.Type: ApplicationFiled: June 15, 2004Publication date: December 30, 2004Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Publication number: 20040259339Abstract: In order to provide a light oxidation process technique for use in a CMOS LSI employing a polymetal gate structure and a dual gate structure, so that both oxidation of a refractory metal film constituting a part of a gate electrode and diffusion of boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode can be prevented, a mixed gas containing a hydrogen gas and steam synthesized from an oxygen gas and a hydrogen gas is supplied to a major surface of a semiconductor wafer A1, and a heat treatment for improving a profile of a gate insulating film that has been cut by etching under an edge part of the gate electrode is conducted under a low thermal load condition in that the refractor metal film is substantially not oxidized, and boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode is not diffused to the semiconductor substrate through the gate oxide film.Type: ApplicationFiled: July 22, 2004Publication date: December 23, 2004Inventors: Yoshikazu Tanabe, Naoki Yamamoto, Shinichiro Mitani, Yuko Hanaoka
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Patent number: 6809399Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: GrantFiled: November 26, 2002Date of Patent: October 26, 2004Assignees: Renesas Technology Corp., Hitachi ULSI Systems Co., Ltd.Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Patent number: 6784038Abstract: In order to provide a light oxidation process technique for use in a CMOS LSI employing a polymetal gate structure and a dual gate structure, so that both oxidation of a refractory metal film constituting a part of a gate electrode and diffusion of boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode can be prevented, a mixed gas containing a hydrogen gas and steam synthesized from an oxygen gas and a hydrogen gas is supplied to a major surface of a semiconductor wafer A1, and a heat treatment for improving a profile of a gate insulating film that has been cut by etching under an edge part of the gate electrode is conducted under a low thermal load condition in that the refractor metal film is substantially not oxidized, and boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode is not diffused to the semiconductor substrate through the gate oxide film.Type: GrantFiled: August 15, 2001Date of Patent: August 31, 2004Assignee: Renesas Technology Corp.Inventors: Yoshikazu Tanabe, Naoki Yamamoto, Shinichiro Mitani, Yuko Hanaoka
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Patent number: 6727152Abstract: A semiconductor device having a field effect transistor formed in a semiconductor layer provided on an insulating layer is provided with a body electrode electrically connected to a channel forming region of the field effect transistor, and a back gate electrode provided below the insulating layer so as to be opposed to the channel forming region of the field effect transistor. A potential for controlling carriers of conduction type opposite to a channel formed in an upper portion of the channel forming region of the field effect transistor is applied to each of the body electrode and the back gate electrode. Thus, the withstand voltage for the drain of the field effect transistor can be increased. It is also possible to stabilize the threshold voltage of the field effect transistor. Furthermore, the threshold voltage of the field effect transistor can be changed in a stable state.Type: GrantFiled: February 28, 2002Date of Patent: April 27, 2004Assignee: Renesas Technology CorporationInventors: Shinichiro Mitani, Takahide Ikeda, Kazutaka Mori, Hisayuki Higuchi
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Patent number: 6706582Abstract: An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel type MISFET is to be formed, vertically with respect to a main surface of a semiconductor to form a first p-type pocket layer. Subsequently, an impurity of a p conduction type is implanted into a region between the n-type diffusion region and the first p-type pocket layer obliquely relative to the main surface of the semiconductor substrate to form a second p-type pocket layer. In this arrangement, the concentration of the impurity ion forming the second p-type pocket layer is made higher than the concentration of the impurity ion used to form the first p-type pocket layer.Type: GrantFiled: May 17, 2002Date of Patent: March 16, 2004Assignee: Renesas Technology CorporationInventors: Youhei Yanagida, Katsuhiko Ichinose, Tomohiro Saito, Shinichiro Mitani
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Publication number: 20030169808Abstract: A communication system is provided including a transceiver and an application controller to transmit and receive signals through the transceiver. An isolator which insulates and separates the transceiver and application controller includes primary and secondary side circuits insulated from each other on a substrate and a capacitive insulating means to transfer signals between the primary and second sides while insulating and separating the primary side circuit from the secondary side circuit.Type: ApplicationFiled: March 4, 2003Publication date: September 11, 2003Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
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Patent number: 6603807Abstract: An isolator is made monolithic by forming a capacitive insulating barrier using an interlayer insulation film on the semiconductor substrate to miniaturize the modem device by the monolithic isolator.Type: GrantFiled: February 26, 1999Date of Patent: August 5, 2003Assignee: Hitachi, Ltd.Inventors: Seigoh Yukutake, Yasuyuki Kojima, Minehiro Nemoto, Masatsugu Amishiro, Takayuki Iwasaki, Shinichiro Mitani, Katsuhiro Furukawa, Chiyoshi Kamada, Atsuo Watanabe, Takayuki Oouchi, Nobuyasu Kanekawa
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Publication number: 20030132465Abstract: An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel type MISFET is to be formed, vertically with respect to a main surface of a semiconductor to form a first p-type pocket layer. Subsequently, an impurity of a p conduction type is implanted into a region between the n-type diffusion region and the first p-type pocket layer obliquely relative to the main surface of the semiconductor substrate to form a second p-type pocket layer. In this arrangement, the concentration of the impurity ion forming the second p-type pocket layer is made higher than the concentration of the impurity ion used to form the first p-type pocket layer.Type: ApplicationFiled: January 28, 2003Publication date: July 17, 2003Applicant: Hitachi, Ltd.Inventors: Youhei Yanagida, Katsuhiko Ichinose, Tomohiro Saito, Shinichiro Mitani
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Publication number: 20030122159Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes;of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.Type: ApplicationFiled: November 26, 2002Publication date: July 3, 2003Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya lida, Akihiro Shimizu
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Patent number: 6548885Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.Type: GrantFiled: January 8, 2001Date of Patent: April 15, 2003Assignee: Hitachi, Ltd.Inventors: Shuji Ikeda, Toshiaki Yamanaka, Kenichi Kikushima, Shinichiro Mitani, Kazushige Sato, Akira Fukami, Masaya Iida, Akihiro Shimizu
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Publication number: 20030032226Abstract: An impurity ion of a polarity opposite to that of an impurity ion forming an n-type diffusion layer is implanted into a lower portion of the n-type diffusion region in a region, in which n-channel type MISFET is to be formed, vertically with respect to a main surface of a semiconductor to form a first p-type pocket layer. Subsequently, an impurity of a p conduction type is implanted into a region between the n-type diffusion region and the first p-type pocket layer obliquely relative to the main surface of the semiconductor substrate to form a second p-type pocket layer. In this arrangement, the concentration of the impurity ion forming the second p-type pocket layer is made higher than the concentration of the impurity ion used to form the first p-type pocket layer.Type: ApplicationFiled: May 17, 2002Publication date: February 13, 2003Applicant: Hitachi, Ltd.Inventors: Youhei Yanagida, Katsuhiko Ichinose, Tomohiro Saito, Shinichiro Mitani
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Publication number: 20020096718Abstract: A semiconductor device having a field effect transistor formed in a semiconductor layer provided on an insulating layer is provided with a body electrode electrically connected to a channel forming region of the field effect transistor, and a back gate electrode provided below the insulating layer so as to be opposed to the channel forming region of the field effect transistor. A potential for controlling carriers of conduction type opposite to a channel formed in an upper portion of the channel forming region of the field effect transistor is applied to each of the body electrode and the back gate electrode. Thus, the withstand voltage for the drain of the field effect transistor can be increased. It is also possible to stabilize the threshold voltage of the field effect transistor. Furthermore, the threshold voltage of the field effect transistor can be changed in a stable state.Type: ApplicationFiled: February 28, 2002Publication date: July 25, 2002Inventors: Shinichiro Mitani, Takahide Ikeda, Kazutaka Mori, Hisayuki Higuchi
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Patent number: 6392277Abstract: A semiconductor device having a field effect transistor formed in a semiconductor layer provided on an insulating layer is provided with a body electrode electrically connected to a channel forming region of the field effect transistor, and a back gate electrode provided below the insulating layer so as to be opposed to the channel forming region of the field effect transistor. A potential for controlling carriers of conduction type opposite to a channel formed in an upper portion of the channel forming region of the field effect transistor is applied to each of the body electrode and the back gate electrode. Thus, the withstand voltage for the drain of the field effect transistor can be increased. It is also possible to stabilize the threshold voltage of the field effect transistor. Furthermore, the threshold voltage of the field effect transistor can be changed in a stable state.Type: GrantFiled: May 19, 2000Date of Patent: May 21, 2002Assignee: Hitachi, Ltd.Inventors: Shinichiro Mitani, Takahide Ikeda, Kazutaka Mori, Hisayuki Higuchi