Abstract: In order to provide a light oxidation process technique for use in a CMOS LSI employing a polymetal gate structure and a dual gate structure, so that both oxidation of a refractory metal film constituting a part of a gate electrode and diffusion of boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode can be prevented, a mixed gas containing a hydrogen gas and steam synthesized from an oxygen gas and a hydrogen gas is supplied to a major surface of a semiconductor wafer A1, and a heat treatment for improving a profile of a gate insulating film that has been cut by etching under an edge part of the gate electrode is conducted under a low thermal load condition in that the refractor metal film is substantially not oxidized, and boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode is not diffused to the semiconductor substrate through the gate oxide film.

Abstract: In order to provide a light oxidation process technique for use in a CMOS LSI employing a polymetal gate structure and a dual gate structure, so that both oxidation of a refractory metal film constituting a part of a gate electrode and diffusion of boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode can be prevented, a mixed gas containing a hydrogen gas and steam synthesized from an oxygen gas and a hydrogen gas is supplied to a major surface of a semiconductor wafer A1, and a heat treatment for improving a profile of a gate insulating film that has been cut by etching under an edge part of the gate electrode is conducted under a low thermal load condition in that the refractory metal film is substantially not oxidized, and boron contained in a p-type polycrystalline silicon film constituting a part of the gate electrode is not diffused to the semiconductor substrate through the gate oxide film.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A method of manufacturing a semiconductor integrated circuit wherein a patterned wafer polishing machine for uniformly polishing a surface by chemical mechanical polishing is utilized which is provided with a head for holding a wafer and rubbing it on an abrasive surface. A pressure plate provided with vents is held by the head body which is provided with a gas inlet and an elastic film for sealing vents is provided on the end face on the side reverse to the gas inlet side of the pressure plate. A patterned wafer is held by the head as the wafer, pressed by action of the pressure of air from the gas inlet via the elastic film is pressed mechanically by the pressure plate. The polishing surface which is a principal plane on the patterned side of the wafer is mechanochemically polished by the abrasive surface.

Abstract: A method of fabricating a semiconductor device is provided wherein a first semiconductor substrate is prepared with a first insulating film formed over a first main surface of the first semiconductor substrate, s semiconductor film of n-type conductivity formed over the first insulating film, and a second insulating film formed over the semiconductor film so as to cover the first main surface. A second semiconductor substrate is also prepared with a third insulating film formed over the second semiconductor substrate. Next, the second insulating film and third insulating films are bonded together by thermal processing to join the first semiconductor substrate and the second semiconductor substrate. A portion of a second main surface of said first semiconductor substrate, opposite to said first main surface of the first semiconductor substrate is then removed to expose a portion of the first semiconductor substrate, thereby providing a semiconductor layer.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacity element. Moreover, the capacity element is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using resistance lowering means such as silicification. In addition, there are made common the means for lowering the resistance of the gate electrode of the transfer MISFETs and the means for forming the local wiring lines.

Abstract: A SRAM of complete CMOS type having its memory cell composed of six MISFETs, in which a pair of local wiring lines for connecting the input/output terminals of CMOS inverters are formed of a refractory metal silicide layer formed over a first conducting layer constituting the individual gate electrodes of the drive MISFETs, the transfer MISFETs and the load MISFETs of the memory cell and in which a reference voltage line formed over the local wiring lines is arranged to be superposed over the local wiring lines to form a capacitor. The capacitor is formed between the local wiring lines and the first conducting layer by superposing the local wiring lines over the first conducting layer. Moreover, the local wiring lines are formed by using a structure with decreased resistance such as silicided structure. In addition, there are made common the processing for lowering the resistance of the gate electrode of the transfer MISFETs and the processing for forming the local wiring lines.

Abstract: Disclosed is a semiconductor device having grooves extending from the semiconductor substrate surface into the interior of the substrate, the grooves having an insulating layer, such as an oxide layer, on the surfaces thereof, with the insulating layer being covered with a conductive layer. The corners of the grooves are rounded-off, whereby the electrostatic destruction voltage of the insulating film is increased as compared with using grooves without having rounded-off corners. Also disclosed is a method of making such device, including steps of forming an initial insulating film on the surfaces of the grooves and removing such initial insulating film to expose surfaces of the grooves, the grooves thereby being provided with rounded-off corners, and then sequentially forming an insulating layer and then a conductive layer on the surfaces of the grooves.