Patents by Inventor Shinichiro Yagi

Shinichiro Yagi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12243947
    Abstract: Distance measurement accuracy is improved.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: March 4, 2025
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shinichiro Yagi, Toshifumi Wakano
  • Publication number: 20250031484
    Abstract: An avalanche photodiode sensor according to an embodiment includes a first semiconductor substrate and a second semiconductor substrate bonded to a first surface of the first semiconductor substrate, wherein the first semiconductor substrate includes a plurality of photoelectric conversion portions arranged in a matrix and an element separation portion for element-separating the plurality of photoelectric conversion portions from each other, the plurality of photoelectric conversion portions include a first photoelectric conversion portion, the element separation portion has a first element separation region and a second element separation region, the first photoelectric conversion portion is arranged between the first element separation region and the second element separation region, the first semiconductor substrate further includes a plurality of concave-convex portions arranged on a second surface opposite to the first surface and arranged between the first element separation region and the second elemen
    Type: Application
    Filed: October 4, 2024
    Publication date: January 23, 2025
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shinichiro YAGI, Toshifumi WAKANO
  • Patent number: 12199114
    Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving the accuracy of phase difference detection while suppressing degradation of a picked-up image. There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion. The present technology is applicable to, for example, a CMOS image sensor including a pixel for detecting the phase difference.
    Type: Grant
    Filed: October 10, 2023
    Date of Patent: January 14, 2025
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shouichirou Shiraishi, Takuya Maruyama, Shinichiro Yagi, Shohei Shimada, Shinya Sato
  • Publication number: 20240373140
    Abstract: An imaging device according to an embodiment of the present disclosure includes: a plurality of pixel blocks each including a plurality of light-receiving pixels including color filters of same color, the plurality of light-receiving pixels being divided into a plurality of first pixel pairs each including two light-receiving pixels adjacent to each other in a first direction; a plurality of lenses provided at respective positions corresponding to the plurality of first pixel pairs; and a plurality of floating diffusion layers each disposed at a boundary between the two light-receiving pixels, of the plurality of first pixel pairs, adjacent to each other in the first direction, the plurality of floating diffusion layers each shared in the plurality of first pixel pairs.
    Type: Application
    Filed: June 17, 2022
    Publication date: November 7, 2024
    Inventors: Masaaki Yanagida, Kazuhiro Yoneda, Takeyoshi Komoto, Kyosuke Ito, Yusuke Otake, Junji Mori, Toshifumi Wakano, Tatsuki Hinamoto, Shinichiro Yagi
  • Patent number: 12034017
    Abstract: A sensor chip and an electronic device with SPAD pixels each including an avalanche photodiode element. The sensor chip includes a pixel area having an array of pixels, an avalanche photodiode element that amplifies a carrier by a high electric field area provided for the each of the pixels, an inter-pixel separation section that insulates and separates each of the pixels from adjacent pixels, and a wiring in a wiring layer laminated on a surface opposite to a light receiving surface of the semiconductor substrate that covers at least the high electric field area. The pixel array includes a dummy pixel area located near a peripheral edge of the pixel area. A cathode and an anode electric potential of the avalanche photodiode element arranged in the dummy pixel area are the same, or at least one of the cathode and anode electric potential is in a floating state.
    Type: Grant
    Filed: April 13, 2023
    Date of Patent: July 9, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shinichiro Yagi, Yusuke Otake, Kyosuke Ito
  • Patent number: 12027540
    Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving the accuracy of phase difference detection while suppressing degradation of a picked-up image. There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion. The present technology is applicable to, for example, a CMOS image sensor including a pixel for detecting the phase difference.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: July 2, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shouichirou Shiraishi, Takuya Maruyama, Shinichiro Yagi, Shohei Shimada, Shinya Sato
  • Publication number: 20240038791
    Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving the accuracy of phase difference detection while suppressing degradation of a picked-up image. There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion. The present technology is applicable to, for example, a CMOS image sensor including a pixel for detecting the phase difference.
    Type: Application
    Filed: October 10, 2023
    Publication date: February 1, 2024
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shouichirou SHIRAISHI, Takuya MARUYAMA, Shinichiro YAGI, Shohei SHIMADA, Shinya SATO
  • Patent number: 11888001
    Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving the accuracy of phase difference detection while suppressing degradation of a picked-up image. There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion. The present technology is applicable to, for example, a CMOS image sensor including a pixel for detecting the phase difference.
    Type: Grant
    Filed: March 31, 2023
    Date of Patent: January 30, 2024
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shouichirou Shiraishi, Takuya Maruyama, Shinichiro Yagi, Shohei Shimada, Shinya Sato
  • Publication number: 20230253420
    Abstract: A sensor chip and an electronic device with SPAD pixels each including an avalanche photodiode element. The sensor chip includes a pixel area having an array of pixels, an avalanche photodiode element that amplifies a carrier by a high electric field area provided for the each of the pixels, an inter-pixel separation section that insulates and separates each of the pixels from adjacent pixels, and a wiring in a wiring layer laminated on a surface opposite to a light receiving surface of the semiconductor substrate that covers at least the high electric field area. The pixel array includes a dummy pixel area located near a peripheral edge of the pixel area. A cathode and an anode electric potential of the avalanche photodiode element arranged in the dummy pixel area are the same, or at least one of the cathode and anode electric potential is in a floating state.
    Type: Application
    Filed: April 13, 2023
    Publication date: August 10, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shinichiro YAGI, Yusuke OTAKE, Kyosuke ITO
  • Publication number: 20230238404
    Abstract: There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion.
    Type: Application
    Filed: March 31, 2023
    Publication date: July 27, 2023
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shouichirou SHIRAISHI, Takuya MARUYAMA, Shinichiro YAGI, Shohei SHIMADA, Shinya SATO
  • Patent number: 11688747
    Abstract: There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: June 27, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shouichirou Shiraishi, Takuya Maruyama, Shinichiro Yagi, Shohei Shimada, Shinya Sato
  • Patent number: 11670649
    Abstract: A sensor chip and an electronic device with SPAD pixels each including an avalanche photodiode element. The sensor chip includes a pixel area having an array of pixels, an avalanche photodiode element that amplifies a carrier by a high electric field area provided for the each of the pixels, an inter-pixel separation section that insulates and separates each of the pixels from adjacent pixels, and a wiring in a wiring layer laminated on a surface opposite to a light receiving surface of the semiconductor substrate that covers at least the high electric field area. The pixel array includes a dummy pixel area located near a peripheral edge of the pixel area. A cathode and an anode electric potential of the avalanche photodiode element arranged in the dummy pixel area are the same, or at least one of the cathode and anode electric potential is in a floating state.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: June 6, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shinichiro Yagi, Yusuke Otake, Kyosuke Ito
  • Publication number: 20220181366
    Abstract: A sensor chip and an electronic device with SPAD pixels each including an avalanche photodiode element. The sensor chip includes a pixel area having an array of pixels, an avalanche photodiode element that amplifies a carrier by a high electric field area provided for the each of the pixels, an inter-pixel separation section that insulates and separates each of the pixels from adjacent pixels, and a wiring in a wiring layer laminated on a surface opposite to a light receiving surface of the semiconductor substrate that covers at least the high electric field area. The pixel array includes a dummy pixel area located near a peripheral edge of the pixel area. A cathode and an anode electric potential of the avalanche photodiode element arranged in the dummy pixel area are the same, or at least one of the cathode and anode electric potential is in a floating state.
    Type: Application
    Filed: March 16, 2020
    Publication date: June 9, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shinichiro YAGI, Yusuke OTAKE, Kyosuke ITO
  • Publication number: 20220140156
    Abstract: Distance measurement accuracy is improved.
    Type: Application
    Filed: February 6, 2020
    Publication date: May 5, 2022
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shinichiro YAGI, Toshifumi WAKANO
  • Publication number: 20210313362
    Abstract: There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion.
    Type: Application
    Filed: June 22, 2021
    Publication date: October 7, 2021
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shouichirou SHIRAISHI, Takuya MARUYAMA, Shinichiro YAGI, Shohei SHIMADA, Shinya SATO
  • Patent number: 11075236
    Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving the accuracy of phase difference detection while suppressing degradation of a picked-up image. There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion. The present technology is applicable to, for example, a CMOS image sensor including a pixel for detecting the phase difference.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: July 27, 2021
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Shouichirou Shiraishi, Takuya Maruyama, Shinichiro Yagi, Shohei Shimada, Shinya Sato
  • Publication number: 20200235149
    Abstract: The present technology relates to a solid-state imaging device and an electronic apparatus capable of improving the accuracy of phase difference detection while suppressing degradation of a picked-up image. There is provided a solid-state imaging device including: a pixel array unit, a plurality of pixels being two-dimensionally arranged in the pixel array unit, a plurality of photoelectric conversion devices being formed with respect to one on-chip lens in each of the plurality of pixels, a part of at least one of an inter-pixel separation unit formed between the plurality of pixels and an inter-pixel light blocking unit formed between the plurality of pixels protruding toward a center of the corresponding pixel in a projecting shape to form a projection portion. The present technology is applicable to, for example, a CMOS image sensor including a pixel for detecting the phase difference.
    Type: Application
    Filed: May 28, 2018
    Publication date: July 23, 2020
    Applicant: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Shouichirou SHIRAISHI, Takuya MARUYAMA, Shinichiro YAGI, Shohei SHIMADA, Shinya SATO
  • Patent number: 10460983
    Abstract: A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: October 29, 2019
    Assignee: SHIN-ETSU HANDOTAI CO.,LTD.
    Inventors: Taishi Wakabayashi, Kenji Meguro, Masatake Nakano, Shinichiro Yagi, Tomosuke Yoshida
  • Publication number: 20170040210
    Abstract: A method for manufacturing a bonded SOI wafer by bonding a bond wafer and a base wafer, each composed of a silicon single crystal, via an insulator film, including the steps of: depositing a polycrystalline silicon layer on the bonding surface side of the base wafer, polishing a surface of the polycrystalline silicon layer, forming the insulator film on the bonding surface of the bond wafer, bonding the polished surface of the polycrystalline silicon layer of the base wafer and the bond wafer via the insulator film, and thinning the bonded bond wafer to form an SOI layer; As a result, it is possible to provide a method for manufacturing a bonded SOI wafer which can prevent single-crystallization of polycrystalline silicon while suppressing an increase of the warpage of a base wafer even when the polycrystalline silicon layer to function as a carrier trap layer is deposited sufficiently thick.
    Type: Application
    Filed: March 4, 2015
    Publication date: February 9, 2017
    Applicant: SHIN-ETSU HANDOTAI CO., LTD.
    Inventors: Taishi WAKABAYASHI, Kenji MEGURO, Masatake NAKANO, Shinichiro YAGI, Tomosuke YOSHIDA
  • Patent number: 9152064
    Abstract: A method of preparing a developer includes mixing a carrier and a powder with each other while falling with gravity.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: October 6, 2015
    Assignee: Ricoh Company, Ltd.
    Inventors: Kousuke Suzuki, Yuuki Mizutani, Shinichiro Yagi