Patents by Inventor Shinji Abe
Shinji Abe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090170225Abstract: A method for manufacturing a semiconductor light emitting device includes forming an insulating film on a semiconductor substrate, the insulating film having an opening therein, forming a Pd electrode in the opening and on the insulating film, and removing the portion of the Pd electrode on the insulating film by the application of a physical force to the portion, while leaving the Pd electrode in the opening.Type: ApplicationFiled: December 10, 2008Publication date: July 2, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takafumi Oka, Masatsugu Kusunoki, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
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Publication number: 20090130790Abstract: A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in an ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating.Type: ApplicationFiled: November 5, 2008Publication date: May 21, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
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Publication number: 20090127661Abstract: Semiconductor devices, in particular nitride semiconductor devices for use in the manufacture of laser diodes, prevent peeling-off of the electrode, and at the same time reduces the complexity of processes and a reduction in yield. A nitride semiconductor device according to the invention includes a P-type nitride semiconductor layer with a ridge on its surface, an SiO2 film covering at least the side face of the ridge, an adherence layer formed on a surface of the SiO2 film and composed mainly of silicon, and a P-type electrode formed on the upper surface of the ridge and on a surface of the adherence layer.Type: ApplicationFiled: November 17, 2008Publication date: May 21, 2009Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Katsuomi Shiozawa, Kyozo Kanamoto, Toshiyuki Oishi, Hiroshi Kurokawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
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Patent number: 7472205Abstract: A communication controller of the present invention includes a descriptor cache mechanism which makes a virtual descriptor gather list from the descriptor indicted from a host, and which allows a processor to refer to a portion of the virtual descriptor gather list in a descriptor cache window. Another communication controller of the present invention includes a second processor which allocates any communication process related with a first communication unit of the communication processes to the first one of a first processors and any communication process related with a second communication unit of the communication processes to the second one of the first processors. Another communication controller includes a first memory which stores control information. The first memory includes a first area accessed by the associated one of processors to refer to the control information and a second area which stores the control information during the access.Type: GrantFiled: April 17, 2003Date of Patent: December 30, 2008Assignee: NEC CorporationInventor: Shinji Abe
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Publication number: 20080293176Abstract: A method for manufacturing a semiconductor optical device includes: forming a first resist pattern on top surface of a laminated semiconductor structure; forming channels and a waveguide ridge by dry etching using the first resist pattern as a mask; forming an SiO2 film on the waveguide ridge and the channels, leaving the first resist pattern on a top surface of the waveguide ridge; forming a second resist pattern covering the SiO2 film on the channels, and exposing the top surface of the SiO2 film on top of the waveguide ridge; removing the SiO2 film by dry etching using the second resist pattern as a mask; removing the first and second resist patterns by a wet method; and forming a p-side electrode.Type: ApplicationFiled: February 28, 2008Publication date: November 27, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Takafumi Oka, Shinji Abe
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Patent number: 7441150Abstract: A fault tolerant (FT) computer system includes a primary system and a secondary system. The primary system includes a first CPU; a first FT control section connected with the first CPU; and a first south bridge connected electrically and operatively with the first FT control section. The secondary system includes a second CPU; a second FT control section connected with the second CPU; and a second south bridge connected electrically with the second FT control section and not connected operatively with the second FT control section. The first FT control section and the second FT control section are connected by a link section, and the primary system and the secondary system operate in synchronization with each other by using the link section, except for the second south bridge.Type: GrantFiled: December 20, 2005Date of Patent: October 21, 2008Assignee: NEC CorporationInventor: Shinji Abe
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Publication number: 20080233668Abstract: A method for manufacturing a semiconductor optical device includes: forming a laminated semiconductor structure of GaN-based materials on a semiconductor wafer, the laminated semiconductor structure forming a laser diode of GaN-based materials, including an active layer having a quantum well structure; cleaving the semiconductor wafer including the laminated semiconductor structure to expose a cleaved end face of the laminated semiconductor structure; and forming an SiO2 film on the cleaved end face and performing a heat treatment to cause Ga vacancy diffusion in the active layer to disorder the quantum well structure of the active layer.Type: ApplicationFiled: March 17, 2008Publication date: September 25, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventor: Shinji Abe
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Publication number: 20080199983Abstract: A method of manufacturing semiconductor laser device including a GaN wafer includes forming a semiconductor layer on the GaN wafer and on which ridge portions are formed. Grooves are formed in the semiconductor layer such that each groove is disposed in line with the scribe marks, between each of the ridge portions and an upstream scribe mark. The grooves are curved and convex outwardly towards a downstream side, and each groove has an apex on a cleavage line. The side extending from the apex preferably does not form an angle of 60 degrees with respect to a cleavage direction or the cleavage line.Type: ApplicationFiled: February 12, 2008Publication date: August 21, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Hitoshi Nakamura, Shinji Abe, Harumi Nishiguchi
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Patent number: 7363311Abstract: A method of mapping a large number of items of contents each having meta-information to a low dimensional space so that the map of the contents reflects the meta-information. The method includes the steps of assigning a concept vector to each item of contents, adjusting the distance between two items of contents so that the closer the classification information of the two items of contents match, the more the distance is reduced, and assigning position information in the low dimensional space to each item of contents based on the adjusted distance.Type: GrantFiled: November 15, 2002Date of Patent: April 22, 2008Assignee: Nippon Telegraph and Telephone CorporationInventors: Etsuro Fujita, Shinji Miyahara, Shinji Abe, Yasuhito Hayashi
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Publication number: 20080090315Abstract: After a metal cap layer is laminated on a semiconductor laminated structure, a waveguide ridge is formed, the waveguide ridge is coated with an SiO2 film, and a resist is applied; then, a resist pattern is formed, the resist pattern exposing the surface of the SiO2 film on the top of the waveguide ridge, and burying the SiO2 film in channels with a resist film having a surface higher than the surface of the metal cap layer of the waveguide ridge and lower than the surface of the SiO2 film of the waveguide ridge; the SiO2 film is removed by dry etching, using the resist pattern as a mask. The metal cap layer is removed by wet etching, and a p-GaN layer of the waveguide ridge is exposed to form the electrode layer.Type: ApplicationFiled: October 8, 2007Publication date: April 17, 2008Applicant: MITSUBISHI ELECTRIC CORPORATIONInventors: Shinji Abe, Kazushige Kawasaki
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Publication number: 20080054277Abstract: The semiconductor laser device includes an active layer, a p-type cladding layer, and a p-type cap layer. The layers are sequentially stacked so that the semiconductor laser device is provided. The p-type cap layer includes both a p-type dopant and an n-type dopant. In another aspect, the p-type cap layer includes a first layer including a first p-type dopant and a second layer including a second p-type dopant having a diffusion coefficient smaller than that of the first p-type dopant. The first layer is far from the active layer, and the second layer is close to the active layer. In further aspect, the p-type cap layer includes carbon (C) as a p-type dopant. According to these configuration, the p-type dopant can be prevented from being diffused in the active layer and the p-type cladding layer.Type: ApplicationFiled: October 25, 2007Publication date: March 6, 2008Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Masayoshi Takemi, Kenichi Ono, Yoshihiko Hanamaki, Chikara Watatani, Tetsuya Yagi, Harumi Nishiguchi, Motoko Sasaki, Shinji Abe, Yasuaki Yoshida
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Patent number: 7294592Abstract: A tent cloth canvas coated on the surface thereof with a photocatalyst, wherein (1) the adhesiveness between a photocatalyst and the tent cloth canvas is kept satisfactorily for an extended time, (2) an anti-fouling capability is kept for a long time, and (3) the photocatalyst carried on the tent cloth canvas does not promote a lowering with time of a tear strength. A tent cloth canvas coated on the surface thereof with a photocatalyst is used, wherein more than 50% in amount of a plasticizer contained in the canvas remains in comparison with that at an initial stage 1500 hours after the canvas is subjected to a sunshine carbon arc type accelerated weathering test as specified in JIS-K5400, or after 3-year outdoor exposure; and a tent clothe canvas having the above properties and structures further contains a plasticizer having a molecular weight of at least 400, and/or a plasticizer migration restricting layer is provided in the middle of the tent cloth and photocatalyst coating layer.Type: GrantFiled: February 8, 2001Date of Patent: November 13, 2007Assignee: Nippon Soda Co., Ltd.Inventors: Shinji Abe, Hiroshi Suzuki, Nobutaka Aimono
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Patent number: 7157540Abstract: The olefinic polymer characterised in that the n-decane-soluble content thereof is 10% by weight or less and the content of a ligand having a cyclopentadienyl structure is 5 ppb by weight or less. The process for producing an olefinic polymer is a process of producing an olefinic polymer by (co)polymerizing olefins in a gas phase using a fluidized-bed reactor, the process comprising: a polymerization step of (co)polymerizing the olefins with allowing a saturated aliphatic hydrocarbon to exist in a concentration of 2 to 30 mol % in the fluidized-bed reactor and a ligand removing step involving a step of bringing the resulting (co)polymer into contact with a ligand-remover and a step of heating said (co)polymer which has been brought into contact with the ligand-remover.Type: GrantFiled: October 11, 2005Date of Patent: January 2, 2007Assignee: Mitsui Chemicals, Inc.Inventors: Satoru Ohtani, Shinji Abe, Hiroto Nishida
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Publication number: 20060150003Abstract: A fault tolerant (FT) computer system includes a first system; and a second system configured to operate in synchronization with the first system. Each of the first and second systems includes a CPU; and a routing controller connected with the CPU. The first system includes a first I/O device as an activist I/O device, and the second system includes a second I/O device as a standby I/O device. The routing controller controls a routing between the CPU and the first I/O device and the second I/O device. When a fault has occurred in the first I/O device, the routing controller in said first system routes a request data a request data received from the CPU and destined to the first I/O device, to the second I/O device.Type: ApplicationFiled: December 16, 2005Publication date: July 6, 2006Inventor: Shinji Abe
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Publication number: 20060150024Abstract: There is disclosed a method capable of resetting a fault tolerant computer in complete synchronization among modules. The method includes a step of generating a reset requesting signal by one of the modules, a step of dividing the reset requesting signal to first and second reset requesting signals, a step of transmitting the second reset requesting signal to the other module, a step of delaying the first reset requesting signal in the one module by a time required for transmitting the second reset requesting signal to the other module, a step of resetting at least one CPU included in the one module by a first CPU reset signal generated based on the first reset requesting signal delayed in the one module, and a step of resetting at least one CPU included in the other module by a second CPU reset signal generated based on the second reset requesting signal transmitted to the other module.Type: ApplicationFiled: December 16, 2005Publication date: July 6, 2006Inventor: Shinji Abe
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Publication number: 20060150005Abstract: A fault tolerant (FT) computer system includes a primary system and a secondary system. The primary system includes a first CPU; a first FT control section connected with the first CPU; and a first south bridge connected electrically and operatively with the first FT control section. The secondary system includes a second CPU; a second FT control section connected with the second CPU; and a second south bridge connected electrically with the second FT control section and not connected operatively with the second FT control section. The first FT control section and the second FT control section are connected by a link section, and the primary system and the secondary system operate in synchronization with each other by using the link section, except for the second south bridge.Type: ApplicationFiled: December 20, 2005Publication date: July 6, 2006Inventor: Shinji Abe
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Publication number: 20060092487Abstract: A video content creating apparatus includes a computer. The computer registers photographic image data input from a photographic input device and meta-information set in relation to the data in a database. After retrieving photographs based on the meta-information, the apparatus selects the photographs to be used for a reminiscence video and decides the reproduction order of the photographs. After registering a BGM playlist, the apparatus reproduces the photographs and BGM for creating the reminiscence video. If there are any regions, the apparatus displays the regions on a monitor while aligning them in sequence according to the meta-information on them. Upon completion of generation (rendering) of a series of reminiscence video contents, the apparatus creates the reminiscence video by saving the rendering results in Flash movie format, for example.Type: ApplicationFiled: October 27, 2005Publication date: May 4, 2006Inventors: Kazuhiro Kuwabara, Noriaki Kuwahara, Kiyoshi Yasuda, Shinji Abe, Nobuji Tetsutani
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Patent number: 7037998Abstract: The olefinic polymer characterised in that the n-decane-soluble content thereof is 10% by weight or less and the content of a ligand having a cyclopentadienyl structure is 5 ppb by weight or less. The process for producing an olefinic polymer is a process of producing an olefinic polymer by (co)polymerizing olefins in a gas phase using a fluidized-bed reactor, the process comprising: a polymerization step of (co)polymerizing the olefins with allowing a saturated aliphatic hydrocarbon to exist in a concentration of 2 to 30 mol % in the fluidized-bed reactor and a ligand removing step involving a step of bringing the resulting (co)polymer into contact with a ligand-remover and a step of heating said (co)polymer which has been brought into contact with the ligand-remover.Type: GrantFiled: March 28, 2003Date of Patent: May 2, 2006Assignee: Mitsui Chemicals, Inc.Inventors: Satoru Ohtani, Shinji Abe, Hiroto Nishida
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Publication number: 20060073335Abstract: A conductive electroless plated powder includes core particles and a nickel film formed by an electroless plating process on the surface of each core particle, wherein crystal grain boundaries are not recognized in the cross section in the direction of the thickness of the nickel film when observed with a scanning electron microscope at a magnification of up to 100,000. A method for making such a conductive electroless plated powder is also disclosed.Type: ApplicationFiled: October 26, 2005Publication date: April 6, 2006Inventors: Masaaki Oyamada, Shinji Abe, Akihiro Kawazoe
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Patent number: 7006442Abstract: In a communication control system for controlling packet transfer conducted by a plurality of logical channels between nodes, a circuit is provided for recording, in a descriptor for recording information regarding transfer by each logical channel, information including a stop bit, an activation bit, the number of logical channel to be activated, an identification value, the number of logical channel to be monitored and a monitoring identification value which are information regarding the order of transfer by each logical channel, and a data link layer includes a circuit for executing transfer by each logical channel based on the order of transfer by each logical channel designated by a descriptor.Type: GrantFiled: November 22, 2000Date of Patent: February 28, 2006Assignee: NEC CorporationInventors: Shinji Abe, Shinji Ueno