Patents by Inventor Shinji Ishida

Shinji Ishida has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5827623
    Abstract: In a halftone type phase shift photomask, a patterned halftone layer is formed on a transparent substrate, and a light screen layer is formed on the halftone layer. A part of a mask pattern is changed from opaque to halftone, thus improving the resist pattern fidelity.
    Type: Grant
    Filed: October 30, 1996
    Date of Patent: October 27, 1998
    Assignee: NEC Corporation
    Inventors: Shinji Ishida, Tadao Yasuzato
  • Patent number: 5792596
    Abstract: In a method of forming a pattern, a photo-mask including a desired pattern is provided. A photo-sensitive resin film is spin-coated on a semiconductor substrate. Subsequently, the surface of the photo-sensitive resin film is changed to have a resistivity against a development solution. Next, light is illuminated to transmit the photo-mask. As a result, the resistivity of only the surface portion of the photo-sensitive resin film corresponding to the desired pattern is decreased based on the property of photo-sensitive resin film by the light having transmitted the photo-mask. Last, the photo-sensitive layer is developed with the development solution.
    Type: Grant
    Filed: February 6, 1996
    Date of Patent: August 11, 1998
    Assignee: NEC Corporation
    Inventors: Tadao Yasuzato, Shinji Ishida, Kunihiko Kasama, Yoko Iwabuchi
  • Patent number: 5774398
    Abstract: Digit lines 31 to 34 and word lines 35 to 38 are provided. NMOS transistors 1 to 4 serving as Y selectors, a memory cell divided into two memory cell groups 25 and 26, a write circuit 21, a sense amplifier 22, a Y decoder 23, an X decoder 24, and a selector for selecting the memory cell groups 25 and 26 are provided in correspondence to the digit and word lines. The selector includes a PMOS transistor 27 and NMOS transistors 28 to 30. The memory cell group 25 is selected when a most significant address bit signal 101 is inputted as "0" level signal, and the memory cell group 26 is selected when the signal 101 is inputted as "1" level signal.
    Type: Grant
    Filed: November 22, 1996
    Date of Patent: June 30, 1998
    Assignee: NEC Corporation
    Inventor: Shinji Ishida
  • Patent number: 5750290
    Abstract: After forming a light shielding layer 2 of ruthenium in a thickness of 70 nm and a reflection preventing layer 3 of a ruthenium oxide in thickness of 30 nm, and a photosensitive resin layer, a sililated layer is formed by electron beam lithography and sililation. Etching is performed for the photosensitive resin layer, and the reflection preventing layer and the light shielding layer are dry etched using oxygen gas with taking the sililated layer as a mask. By this, dimensional precision of a pattern of a photo mask can be improved.
    Type: Grant
    Filed: April 19, 1996
    Date of Patent: May 12, 1998
    Assignee: NEC Corporation
    Inventors: Tadao Yasuzato, Shinji Ishida
  • Patent number: 5742206
    Abstract: A gain control circuit (200) for controlling gain of a circuit (100) operative on the basis of a positive supply voltage, in accordance with strength of current pulled out by the gain control circuit from a control node (12) of the gain-controlled circuit (100), comprises: a depletion-type transistor (21) having one end (drain) connected to the control node of the gain-controlled circuit, the other end (source) connected to a voltage supply terminal (25) to which an external supply voltage is applied, and a gate terminal connected to a control signal terminal (16) to which an external positive voltage control signal is applied; and a resistance element (22) connected in parallel to both ends of the depletion-type transistor (21), for shifting a threshold voltage of the transistor in a positive direction by applying a shift voltage between both the ends of the transistor so that turn-on resistance of the transistor can be controlled on the basis of the positive voltage control signal.
    Type: Grant
    Filed: September 20, 1996
    Date of Patent: April 21, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinji Ishida
  • Patent number: 5500745
    Abstract: A digitized image data produced by reading a certain scanning line portion of a shading correction plate by an image sensor is stored in a buffer memory as digital data B. A digital comparator compares, on a pixel-by-pixel basis, the digital data B with new digital data A produced by reading another scanning line portion apart from the above portion by a distance of a plurality of scanning lines. This comparison is repeated while the reading line portion on the correction plate is changed until a difference between the data B and the new data A becomes smaller than a predetermined value for all the pixels. The data of one scanning line finally stored in the buffer memory is transferred to a shading correction data memory.
    Type: Grant
    Filed: December 8, 1993
    Date of Patent: March 19, 1996
    Assignee: Fuji Xerox Co., Ltd.
    Inventors: Fumio Iishiba, Shinji Ishida, Masatoshi Ikeda, Kunihiro Takahashi
  • Patent number: 5499502
    Abstract: A motor-driven air pump operates when an engine is starting so that warming-up of an exhaust gas purifying catalyst may be expedited. The air pump has a low ventilation resistance to pass secondary air therethrough even when the pump is not driven by the motor. A high-response, low pressure-loss check valve is disposed in a passage connecting the catalyst in the exhaust gas passage and the air pump. When the engine is decelerating, the pump is not driven. However, the secondary air is introduced to the catalyst through the high-response, low pressure-loss check valve from the pump under the negative pressure caused by pulsation of the exhaust gas pressure. Thus, a bad smell from the catalyst may be prevented without increasing the size of the air pump and the motor.
    Type: Grant
    Filed: March 22, 1995
    Date of Patent: March 19, 1996
    Assignee: Nippondenso Co., Ltd.
    Inventors: Yukio Haniu, Shinji Ishida, Michio Koshimizu
  • Patent number: 5411535
    Abstract: A cardiac pacemaker improved to reduce the weight and size and to unburden the wearer of the pacemaker, while ensuring safe transmission of signals. The cardiac pacemaker includes a cardiac pacemaker main body 100 having at least two electrodes for detecting cardio-information, a control section for performing a control by outputting pulses on the basis of the cardio-information, and a transmitting section for modulating the pulses and transmitting the modulated pulses. The pacemaker also has pacing electrode portion having a receiving section for receiving the transmitted pulses and stimulating electrodes activated by the pulses output from the receiving section.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: May 2, 1995
    Assignee: Terumo Kabushiki Kaisha
    Inventors: Tadashi Fujii, Shinji Ishida
  • Patent number: 5248238
    Abstract: A housing 14 forms, together with a cover 34, an annular vortex chamber 42. An impeller 22 is provided with a disk portion 24 which is connected to a drive shaft 12 so that the impeller 22 rotates integrally with the shaft 12. The impeller 22 has an annular support portion 26 and rows of angularly-spaced blade portions 28 and 30 arranged along the circumference of the impeller. The blade portions 28 and 30 are located in the vortex chamber 42. A seal portion is created between the impeller 22, the housing 14 and the cover 34, which seal portion is constructed by inner axial slits 72A and 72B formed between axially-spaced surfaces transverse to the axis of the shaft 12, radial slits 74A and 74B formed between radially spaced-apart cylindrical surfaces, and outer axial slits 76A and 76B formed between axially spaced-apart surfaces transverse to the axis of the shaft 12.
    Type: Grant
    Filed: April 15, 1992
    Date of Patent: September 28, 1993
    Assignee: Nippondenso Co., Ltd.
    Inventors: Shinji Ishida, Kazunori Matsui
  • Patent number: 4967701
    Abstract: A valve timing adjuster according to the present invention, comprises a pulley rotationally connected to one of an output shaft of engine and a cam shaft, a sleeve which is supported on the pulley, which is rotatable within a predetermined angle of rotation on the pulley and which is rotationally connected to the other one of the output shaft of engine and the cam shaft, an electromagnet mounted on one of the pulley and the sleeve, an armature mounted on the other one of the pulley and the sleeve so that magnetic flux including a magnetic flux component extending in the circumferential direction of the valve timing adjuster is generated, the armature is drawn by the magnetic flux toward the electromagnet and the sleeve is rotated within the predetermined angle of rotation on the pulley when the electromagnet is energized, and a control device which controls the operation of electromagnet so that the phase difference between the cam shaft and the output shaft is suitably adjusted during operation of a vehicle.
    Type: Grant
    Filed: January 9, 1990
    Date of Patent: November 6, 1990
    Assignee: Nippondenso Co., Ltd.
    Inventors: Kimiyoshi Isogai, Shinji Ishida, Toshinobu Nishi, Hidenori Sato, Kenji Yamada
  • Patent number: D327740
    Type: Grant
    Filed: January 26, 1990
    Date of Patent: July 7, 1992
    Assignee: Terumo Kabushiki Kaisha
    Inventors: Tetsuya Arioka, Shinji Ishida