Abstract: A parallel processor developing system comprises a control computer, an interface portion, a processing element, a tracer portion and a display portion. The processing element comprises a data driven type processor. The interface portion stores data packets supplied from the control computer and applies the data packets to the processing element at a predetermined time interval. The tracer portion stores the data packets supplied from predetermined ports of the processing element together with time information. The display portion displays storage contents of the tracer portion.

Abstract: A data-driven processor which has a packet assembling unit to add a tag information to the sequentially inputted data when the input data has no tag information, such as destination address or the like, thereby enabling the data to be inputted without using an external circuit, such as a host processor, and improving the data input rate and which also has a packet outputting and rearranging unit for rearranging an output packet stream in a predetermined order to thereby output the data information only, so that it is possible that the data is outputted without any external circuit, such as a host processor, the output rate is improved and the data output is executed in a predetermined order.

Abstract: Novel polyamide copolymers having skeletons of a specific structure are disclosed. The polyamide copolymers have excellent resistance to hydrolysis, low temperature characteristics (low temperature softness), heat aging resistance and mechanical properties as compared to conventional polyamide copolymers. The polyamide copolymers also show excellent efficiencies in fabrication properties and transparency. In particular, the polyamide copolymers having a branched structure in the molecule thereof provide good results.

Abstract: A data driven processing system includes a mechanism for generating a data pair from a sequential input data stream by matching identifier fields. The pairing mechanism comprises a hash memory in which input data words to be paired are stored by using hashed addresses. If a hash collision occurs, the data word which caused the hash collision is transmitted to a counter-directional data loop which is used to generate a data pair. If an input data word is not paired after one pass through the data loop it is returned to the hash memory for another pairing operation. Use of both the hash memory and the counter-directional data loop reduces the required hash memory size and increases processing efficiency.

Abstract: A data transmission apparatus which is connected with a shift register of a plural stages forming a forward path of data transmission line, and a shift register of a plural stages forming a backward path of the same, and a loop-back part therebetween, and comprises bypasses between the shift register on the forward path and on the backward path to bypass the transmitted data when significant data does not exist on the loop-back part side from a stage on which the bypass is comprised and no data stays at a stage where the bypass is comprised, so that data is transmitted at high speed, and which is constructed to be able to control the bypass from external, so that testing of circuitry is easy.

Abstract: A pipelined processor is provided with a plurality of control stages controlling a datapath made up of a plurality of parallel static-type data latches. The latches each include a feedback circuit, typically a field-effect transistor, which is enabled by a data latch control signal from a particular control stage. Enabling the feedback stage consumes power. A data stagnation detection circuit detects a data stagnation in the datapath, by use of handshake control signals exchanged between the control stages. The data stagnation detection circuit inhibits enablement of the feedback circuit when no data stagnation is detected, reducing power used in the latch.

Abstract: A data transmission apparatus for transmitting data between systems includes: an input data transmission path, an output data transmission path, and a branch data transmission path each constituted by a shift register, each data transmission path has a plurality of data storage circuits and a plurality of transfer control circuits each provided corresponding to each o--stage. The data storage circuit control a self stage data storage circuit in accordance with a control signal from the transfer control circuit of an adjacent stage. An initialization circuit for initializing the device is provided so that data on the data transmission path does not remain at the start of operation of the device.

Abstract: In a data flow machine, a program stored in advance is read out based on a tag included in a packet when the packet including first data is inputted from an external portion. Then, an instruction packet is formed by the content read out as a new tag and the first data, so that the instruction packet is outputted. Second data including the same tag as that included in the first data of the instruction packet read out from the program memory is detected. Firing processing is performed with respect to the first data and the second data as a pair and arithmetic processing is performed according to the instruction as a part of the tag included in an arithmetic packet, so that the arithmetic packet is outputted as a packet. The tag included in the packet is determined and the packet is outputted to an external portion or is inputted again to the internal portion.

Abstract: An improved data driven processor that utilizes queue buffers in the data path to maintain optimal dataflow.

Abstract: By providing a tag data renewing unit in a data flow-computer, the "delay" function, which is necessary for a digital filter, etc., can be realized, and it is unnecessary to keep the order relation for tokens with respect to first-in/first-out, which must be kept at respective points in a conventional data flow computer, and thereby the architecture of a compiler can be simplified and at the same time the execution time can be shortened.

Abstract: A data processing apparatus includes two data transmission paths formed likewise in a loop fashion. These data transmission paths include a plurality of latch registers connected in a cascade fashion respectively and are constituted as a so-called self-running type shift register wherein each data word constituting a data packet is shifted in sequence provided that a pre-stage register is vacant. Data packets are transmitted in the directions reverse to each other on the two loop-shaped data transmission paths an identification data included in each data packet being transmitted is detected in a section defined as a data packet pair detecting section. The detected identification data are compared in a comparing circuit and, one new data packet is produced from the two data packets in a manner that a data packet is joined from one data transmission path to the other data transmission path.

Abstract: In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module, and the daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Abstract: In an information processor, input interface units (161, 162) are connected to one ring data bus (191) through jointing units (201, 202) and data processing units (181 and 185) are connected to the ring data bus (191) through jointing units (203 through 206) and branching units (221 through 224). Data processing units (183 through 187) are connected to the other ring data bus (192) through jointing units (207 through 210) and branching units (225 through 228) and output interface units (171, 172) are connected to the other ring data bus (192) through branching units (229, 230). The ring data buses (191, 192) propagate the respective in data through the input interface units (161, 162) while storing such data, and processing the data in any of the data processing units to provide outputs to any of the output interface units (171, 172).

Abstract: A hand-shake type control circuit for controlling a data transfer circuit according to the status of a data transfer request signal. The data transfer request signal is initially received at a NAND gate and is also directly coupled to the reset input of are set flip-flop. The output of the NAND gate is used as a first control signal to set the flip-flop and to cause another circuit to activate data transfer. The flip-flop output is a second control signal which is reset only when the transfer request signal changes from an active to an inactive status. The second control signal is coupled to an input of the NAND gate and inactivates the first control signal. Thus, data transfer cannot recur until after the data transfer request signal changes to an inactive status so that parasitic oscillations are eliminated. The flip-flop consists of two, two input NAND gates that are located out of the path of data transfer and that are easier to fabricate than the prior art D flip-flop.

Abstract: A data transmission system comprises an input data transmission line (1), an output data transmission line (4), a branching data transmission line (5) and a jointing data transmission line (7) formed respectively by asynchronous free-running shift registers using a plurality of data latches (101 to 106, 401 & 402, 501 & 502, 701 & 702) and, C elements (111 to 116, 411 & 412, 511 & 512, 711 & 712) respectively. A branching control circuit 3 supplies data to be branched to the branching data transmission line (5) in response to the decision by a branching decision circuit (2) as to the fact that the data to be branched is transmitted on the input data transmission line (1).

Abstract: A tag data processing apparatus is described for use in a data flow computer utilizing a tagged token scheme. A tag adding process and tag restoring process are executed by using pipeline registers, a queue memory and simple control circuit, thereby obtaining high speed operation and superior throughput without the need for a tag memory table, complicated operation-test circuitry or a sequence control circuit.

Abstract: In a data transmission apparatus, a plurality of data processing modules are used and required sequence setting is performed to a port sequencer of input/output ports of each data processing module. The daisy chain transfer of the selective data transfer, the load distribution data transfer, the collective data transfer is combined between the data processing modules, thereby the data transmission is performed efficiently at high speed.

Abstract: A coincidence element responsive to a plurality of input signals for outputting the level of the input signals when said plurality of input signals coincide with each other includes, a serial connection of a first electrically conductive type and a second electrically conductive type MOS transistors of the same number, the number being equal to the number of the input signals, responsive to said plurality of inputs connected between a first power supply and a second power supply; and a CMOS inverter responsive to an intermediate output at the connection of the most lower stage first conductivity type MOS transistor and the most upper stage second conductivity type MOS transistor for outputting a coincidence signal.

Abstract: A system is provided for separating waste water or solution into a permea solution and a concentrated solution by feeding the waste water or solution to a reverse osmosis apparatus using a membrane.A chemical pretreating apparatus is provided to prevent hard scales contained in the waste water or solution from precipitation during the concentration in the reverse osmosis apparatus using the membrane. An apparatus for charging sponge balls is further provided to mechanically remove suspended solids and other suspended matters, that is, soft scales when deposited on the surface of membrane. The sponge balls are desirably recyclically used.