Abstract: A surface-emission laser diode includes a distributed Bragg reflector tuned to wavelength of 1.1 ?m or longer, wherein the distributed Bragg reflector includes an alternate repetition of a low-refractive index layer and a high-refractive index layer, with a heterospike buffer layer having an intermediate refractive index interposed therebetween with a thickness in the range of 5–50 nm.

Abstract: A psychotic manifestation and mental state evaluation apparatus and method which can individually discriminate among symptoms by taking advantage of stimulating Noh mask images and also evaluate with a high probability whether a person is suffering from a specific symptom at the time of diagnosing, clinical examination, assessment, or counseling.

Abstract: Compositions useful for removing a polymer material from a substrate, such as an electronic device, and methods of using such compositions are provided. These compositions and methods reduce the corrosion of any underlying metal surfaces, and are particularly suited to remove polymer residues from electronic device substrates.

Abstract: A surface-emission laser diode includes a distributed Bragg reflector tuned to a wavelength of 1.

Abstract: A surface-emission laser diode includes a distributed Bragg reflector tuned to wavelength of 1.1 ?m or longer, wherein the distributed Bragg reflector includes an alternate repetition of a low-refractive index layer and a high-refractive index layer, with a heterospike buffer layer having an intermediate refractive index interposed therebetween with a thickness in the range of 5-50 nm.

Abstract: A nonvolatile semiconductor memory apparatus capable of attaining a low voltage when writing data, wherein charge injection into an unnecessary portion is not performed when reading, and capable of unifying a threshold voltage level when erasing, comprising a first conductive type semiconductor region, two source/drain regions made by a second conductive type semiconductor, a plurality of dielectric films stacked on a first conductive type semiconductor region between the two source/drain regions, and a gate electrode; wherein the first conductive type semiconductor region between the two source/drain regions includes a first region wherein a channel is formed by an inversion layer of a minority carrier and a second region formed between the first region and a source/drain region on one side of the first region and having higher concentration than that of the first region.

Abstract: A small antenna comprises an antenna conductor, and a dielectric chip formed at surroundings of the antenna conductor by a plurality of resin moldings.

Abstract: A line-shaped comprises an antenna element in which a strip-shaped conductor is bent in a width direction of a strip, and a chamfered portion is provided on an outer edge of a bent portion of the strip-shaped conductor.

Abstract: A nonvolatile semiconductor memory apparatus capable of attaining a low voltage when writing data, wherein charge injection into an unnecessary portion is not performed when reading, and capable of unifying a threshold voltage level when erasing, comprising a first conductive type semiconductor region, two source/drain regions made by a second conductive type semiconductor, a plurality of dielectric films stacked on a first conductive type semiconductor region between the two source/drain regions, and a gate electrode; wherein the first conductive type semiconductor region between the two source/drain regions includes a first region wherein a channel is formed by an inversion layer of a minority carrier and a second region formed between the first region and a source/drain region on one side of the first region and having higher concentration than that of the first region.

Abstract: Of margins of a resin molding with an antenna element buried therein which lie around the antenna element, a margin on that side of the resin molding where a gate mark remains is made larger than margins on other sides where there is no gate mark. Particularly, when the antenna element has a line antenna portion and a capacitance-adding portion provided at a distal end of the line antenna portion, the resin molding is injection-molded in such a way that a gate mark can be formed on that side where the capacitance-adding portion is located. Those portions of the resin molding where the terminal portions are led out are dented from levels of portions around those portions. This provides a chip antenna which has a simple structure with a high mechanical strength and does not prevent separation or cracking from occurring in the resin molding in which the antenna element is buried and a method of manufacturing the chip antenna.

Abstract: A surface-emission laser diode includes a distributed Bragg reflector tuned to wavelength of 1.1 &mgr;m or longer, wherein the distributed Bragg reflector includes an alternate repetition of a low-refractive index layer and a high-refractive index layer, with a heterospike buffer layer having an intermediate refractive index interposed therebetween with a thickness in the range of 5-50 nm.

Abstract: Of margins of a resin molding with an antenna element buried therein which lie around the antenna element, a margin on that side of the resin molding where a gate mark remains is made larger than margins on other sides where there is no gate mark. Particularly, when the antenna element has a line antenna portion and a capacitance-adding portion provided at a distal end of the line antenna portion, the resin molding is injection-molded in such a way that a gate mark can be formed on that side where the capacitance-adding portion is located. Those portions of the resin molding where the terminal portions are led out are dented from levels of portions around those portions. This provides a chip antenna which has a simple structure with a high mechanical strength and does not prevent separation or cracking from occurring in the resin molding in which the antenna element is buried and a method of manufacturing the chip antenna.

Abstract: A line-shaped comprises an antenna element in which a strip-shaped conductor is bent in a width direction of a strip, and a chamfered portion is provided on an outer edge of a bent portion of the strip-shaped conductor.

Abstract: A method of determining multi-bit data in a multi-level memory. The method includes setting a source potential of a memory cell to a first source potential, setting a gate potential thereof to a first read-out potential, and determining if bit data of a first digit of multi-bit data is “0” or “1”. Also, the method includes setting the source potential of the memory cell to the first source potential and setting the gate potential thereof to a second read-out potential that is different from the first read-out potential when the bit data of the first digit is “0”, and determining if bit data of a second digit of the multi-bit data is “0” or “1”.

Abstract: With a local self boost (LSB) technique, the distribution, of threshold voltages after data erase is set toward a higher side and the distribution width is narrowed sufficiently within the range in which cell erase states can be read. To this end, block write is carried out on a memory cell array. Next, setting a predetermined voltage as a start voltage, soft erase is carried out for each block. After carrying out erase verification read, the threshold voltages of the cells are compared with a determination reference value. As a result of this comparison, if the threshold voltages of the cells do not reach the determination reference value, soft erase is repeated. In that case, the predetermined voltage during the soft erase is changed from the start voltage. When the threshold voltages of all the cells have reached the determination reference value, the soft erase is ended.

Abstract: With a local self boost (LSB) technique, the distribution of threshold voltages after data erase is set toward a higher side and the distribution width is narrowed sufficiently within the range in which cell erase states can be read. To this end, block write is carried out on a memory cell array. Next, setting a predetermined voltage as a start voltage, soft erase is carried out for each block. After carrying out erase verification read, the threshold voltages of the cells are compared with a determination reference value. As a result of this comparison, if the threshold voltages of the cells do not reach the determination reference value, soft erase is repeated. In that case, the predetermined voltage during the soft erase is changed from the start voltage. When the threshold voltages of all the cells have reached the determination reference value, the soft erase is ended.

Abstract: A small antenna comprises an antenna conductor, and a dielectric chip formed at surroundings of the antenna conductor by a plurality of resin moldings.

Abstract: With a local self boost (LSB) technique, the distribution of threshold voltages after data erase is set toward a higher side and the distribution width is narrowed sufficiently within the range in which cell erase states can be read. To this end, block write is carried out on a memory cell array. Next, setting a predetermined voltage as a start voltage, soft erase is carried out for each block. After carrying out erase verification read, the threshold voltages of the cells are compared with a determination reference value. As a result of this comparison, if the threshold voltages of the cells do not reach the determination reference value, soft erase is repeated. In that case, the predetermined voltage during the soft erase is changed from the start voltage. When the threshold voltages of all the cells have reached the determination reference value, the soft erase is ended.

Abstract: With a local self boost (LSB) technique, the distribution of threshold voltages after data erase is set toward a higher side and the distribution width is narrowed sufficiently within the range in which cell erase states can be read. To this end, block write is carried out on a memory cell array. Next, setting a predetermined voltage as a start voltage, soft erase is carried out for each block. After carrying out erase verification read, the threshold voltages of the cells are compared with a determination reference value. As a result of this comparison, if the threshold voltages of the cells do not reach the determination reference value, soft erase is repeated. In that case, the predetermined voltage during the soft erase is changed from the start voltage. When the threshold voltages of all the cells have reached the determination reference value, the soft erase is ended.

Abstract: This invention is a nonvolatile semiconductor memory device including an electrically rewritable memory cell having a gate, source, drain, and charge storage layer, an extracting electrode electrically connected to at least one of the source and drain of the memory cell, and a counter electrode essentially capacitively coupled with the extracting electrode.